TPS65800_07 Datasheet, PDF (29/98 Pages) Texas Instruments – SINGLE-CELL Li-ION BATTERY- AND POWER-MANAGEMENT IC

TPS65800
www.ti.com
SLVS606C – SEPTEMBER 2005 – REVISED FEBRUARY 2007
Table 2. I²C Naming Conventions Used
CONDITION
START sent from host
STOP sent from host
TPS65800 I²C slave address sent from host, bus direction set from host to TPS65800 (WRITE)
TPS65800 register address sent from TPS65800, bus direction is from TPS65800 to host (READ)
Non-valid I²C slave address sent from host
Valid TPS65800 register address sent from host
Non-valid TPS65800 register address sent from host
I/O data byte (8 bits) sent from host to TPS65800
I/O data byte (8 bits) sent from TPS65800 to host
Acknowledge (ACK) from host
Not acknowledge (NACK) from host
Acknowledge (ACK) from TPS65800
Not acknowledge (NACK) from TPS65800
CODE
S
P
hA0
hA1
hA_N
HCMD
HCMD_N
hDATA
bqDATA
hA
hN
bqA
bqN
STOP
START
CONDITION CONDITION
(P)
(S)
BIT 7
MSB
BIT 6
BIT0
LSB
AC(hKANoOrWbqL)AEDGECOSN(TPDO) _IPTION
STOP
CONDITION
(P)
START
CONDITION
(S)
BIT 7
MSB
SCL
SDA
DATA LINE
STABLE
BIT 6
DATA
CHANGE
ALLOWED
SCL
SDA
STOP
START
CONDITION CONDITION
(P)
(S)
BIT 7
MSB
SCL
SDA
BIT 6
BIT 5-1
BIT 0
LSB
NOT
STOP
ACKNOWLEDGE CONDITION
(hN or bqN)
(P)
Figure 24. I²C operation waveforms
For normal data transfers, SDA is allowed to change only when SCL is low, and one clock pulse is used per bit
of data. The SDA line must remain stable whenever the SCL line is high, as SDA changes when SCL is high are
reserved for indicating the start and stop conditions. Each data transfer is initiated with a start condition and
terminated with a stop condition.
When addressed, the TPS65800 device generates an acknowledge bit after the reception of each byte by
pulling the SDA line Low. The master device (microprocessor) must generate an extra clock pulse that is
associated with the acknowledge bit. After the acknowledge/not acknowledge bit the TPS65800 leaves the data
line high, enabling a STOP condition generation.
I²C Read and Write Operations
The TPS65800 supports the standard I²C one byte Write. The basic I²C read protocol has the following steps:
• Host sends a start and sets TPS65800 I²C slave address in write mode.
• TPS65800 ACKs that this is a valid I²C address and that the bus is configured for write.
• Host sends TPS65800 register address.
• TPS65800 ACKs that this is a valid register and stores the register address to be read.
• Host sends a repeated start and TPS65800 I²C slave address, reconfiguring the bus for read.
• TPS65800 ACKs that this is a valid address and that bus is reconfigured.
• Bus is in read mode, TPS65800 starts sending data from selected register.
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