TLV2460 Datasheet, PDF (29/54 Pages) Texas Instruments – FAMILY OF LOW-POWER RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH SHUTDOWN

TLV2460, TLV2461, TLV2462, TLV2463, TLV2464, TLV2465, TLV246xA
FAMILY OF LOWĆPOWER RAILĆTOĆRAIL INPUT/OUTPUT
OPERATIONAL AMPLIFIERS WITH SHUTDOWN
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
macromodel information
APPLICATION INFORMATION
Macromodel information provided was derived using Microsim Parts Release 8, the model generation
software used with Microsim PSpice . The Boyle macromodel (see Note 2) and subcircuit in Figure 54 are
generated using the TLV246x typical electrical and operating characteristics at T_A = 25°C. Using this
information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most
cases):
D Maximum positive output voltage swing
D Maximum negative output voltage swing
D Slew rate
D Quiescent power dissipation
D Input bias current
D Open-loop voltage amplification
D Unity-gain frequency
D Common-mode rejection ratio
D Phase margin
D DC output resistance
D AC output resistance
D Short-circuit output current limit
NOTE 2: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Intergrated Circuit Operational Amplifiers”, IEEE
Journal of Solid-State Circuits, SC-9, 353 (1974).
99
3
VDD ₊
2
IN −
IN +
1
DP
4
GND
ISS
RP
RSS
CSS ^VD
10
J1
J2
DC
11
RD1
12
DE
C1
RD2
VE
EGND ₊
R2
+
9
+
−
VB
53
−
−
6
GCM
FB
C2
GA
RO2
7
+
VLIM
−
8
RO1
DLN
92
54
90
91
+
HLIM
+ _DLP
+
VLP
−
VLN
−
−
−
+
OUT
5
.SUBCKT TLV246X 1 2 3 4 5
C1
11 12 2.46034E−12
C2
6 7 10.0000E−12
CSS 10 99 443.21E−15
DC
5 53 DY
DE
54 5 DY
DLP 90 91 DX
DLN 92 90 DX
DP
4 3 DX
EGND 99 0 POLY (2) (3,0) (4,0) 0 .5 .5
FB
7 99 POLY (5) VB VC VE VLP
+ VLN 0 21.600E6 −1E3 1E3 22E6 −22E6
GA
6 0 11 12 345.26E−6
GCM 0 6 10 99 15.4226E−9
ISS
10 4 DC 18.850E−6
HLIM 90 0 VLIM 1K
J1
11 2 10 JX1
J2
12 1 10 JX2
R2
6 9 100.00E3
RD1 3 11 2.8964E3
RD2 3 12 2.8964E3
R01
8 5 5.6000
R02
7 99 6.2000
RP
3 4 8.9127
RSS 10 99 10.610E6
VB
9 0 DC 0
VC
3 53 DC .7836
VE
54 4 DC .7436
VLIM 7 8 DC 0
VLP
91 0 DC 117
VLN 0 92 DC 117
.MODEL DX D (IS=800.00E−18)
.MODEL DY D (IS=800.00E−18 Rs = 1m Cjo=10p)
.MODEL JX1 NJF (IS=1.0000E−12 BETA=6.3239E−3
+ VTO= −1)
.MODEL JX2 NJF (IS=1.0000E−12 BETA=6.3239E−3
+ VTO= −1)
.ENDS
Figure 54. Boyle Macromodels and Subcircuit
PSpice and Parts are trademarks of MicroSim Corporation.
WWW.TI.COM
29