SN74V215_06 Datasheet, PDF (29/43 Pages) Texas Instruments – 512 X 18, 1024 X 18, 2048 X 18, 4096 X 18 DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES

SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
tCLK
WCLK
tCLKH
1
tCLKL
2
tDS
D0–D17 ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ^DVaatalidin ÌÌ^tÌÌ^DH ÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
WEN
ÎÎÎÎÎÎ ÏÏÏÏÏÏ ÎÎÎÎ ^tENS
tENH
No Operation
tWFF
tWFF
FF
tSKEW1
(see Note A)
RCLK
REN
NOTES: A. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to ensure that FF goes high after one WCLK
cycle plus tRFF. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, the FF deassertion
might be delayed an extra WCLK cycle.
B. LD is high.
C. Select double register-buffered standard mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during reset.
Figure 21. Write-Cycle Timing With Double Register-Buffered FF (Standard Mode)
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