LMK04826B Datasheet, PDF (29/101 Pages) Texas Instruments – LMK0482xB Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs

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LMK04826B, LMK04828B
SNAS605 AP – MARCH 2013 – REVISED JUNE 2013
4.5 Frequency Holdover
The LMK04820 family supports holdover operation to keep the clock outputs on frequency with minimum
drift when the reference is lost until a valid reference clock signal is re-established.
4.6 PLL2 Integrated Loop Filter Poles
The LMK04820 family features programmable 3rd and 4th order loop filter poles for PLL2. These internal
resistors and capacitor values may be selected from a fixed range of values to achieve either a 3rd or 4th
order loop filter response. The integrated programmable resistors and capacitors compliment external
components mounted near the chip.
These integrated components can be effectively disabled by programming the integrated resistors and
capacitors to their minimum values.
4.7 Internal VCOs
The LMK04820 family has two internal VCOs, selected by VCO_MUX. The output of the selected VCO is
routed to the Clock Distribution Path. This same selection is also fed back to the PLL2 phase detector
through a prescaler and N-divider.
4.8 External VCO Mode
The Fin/Fin* input allows an external VCO to be used with PLL2 of the LMK04820 family.
Using an external VCO reduces the number of available clock inputs by one.
4.9 Clock Distribution
The LMK04820 family features a total of 14 PLL2 clock outputs driven from the internal or external VCO.
All PLL2 clock outputs have programmable output types. They can be programmed to LVPECL, LVDS, or
HSDS, or LCPECL.
If OSCout is included in the total number of clock outputs the LMK04820 family is able to distribute, then
up to 15 differential clocks. OSCout may be a buffered version of OSCin, DCLKout6, DCLKout8, or
SYSREF.
The following sections discuss specific features of the clock distribution channels that allow the user to
control various aspects of the output clocks.
4.9.1 DEVICE CLOCK DIVIDER
Each device clock, DCLKoutX, has a single clock output divider. The divider supports a divide range of 1
to 32 (even and odd) with 50% output duty cycle using duty cycle correction mode. The output of this
divider may also be directed to SDCLKoutY, where Y = X + 1.
4.9.2 SYSREF CLOCK DIVIDER
The SYSREF clocks, SDCLKoutY, all share a common divider. The divider supports a divide range of 8 to
8191 (even and odd).
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