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| ADS7947 Datasheet, PDF (29/38 Pages) Texas Instruments – 12/10/8-Bit 2MSPS, Dual-Channel Unipolar Pseudo-Differential Ultralow-Power SAR Analog-to-Digital Converters | |||
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ADS7947
ADS7948
ADS7949
SLAS708 â SEPTEMBER 2010
The device sampling rate can be maximized by using a 34MHz clock even for lower throughputs. Table 2 shows
typical calculations for the ADS7947(12-bit).
Table 2. Sampling Frequency versus Source Impedance for the ADS7947 (12-Bit)
RSOURCE (Ω)
180
250
1000
5000
CBYPASS (pF)
10
10
10
10
SAMPLING TIME,
tACQ (ns)
80
107
422
2102
CONVERSION TIME,
tCONV (ns)
397
(with 34MHz clock)
CYCLE TIME, tACQ +
tCONV (ns)
477
397
(with 34MHz clock)
504
397
(with 34MHz clock)
819
397
(with 34MHz clock)
2499
SAMPLING RATE
(MSPS)
2
1.98
1.2
0.4
It is necessary to allow 1000ns additional sampling time over what is shown in Table 2 if PDEN (pin 12) is set
high.
PCB LAYOUT/SCHEMATIC GUIDELINES
ADCs are mixed-signal devices. For maximum performance, proper decoupling, grounding, and proper
termination of digital signals is essential. Figure 54 shows the essential components around the ADC. All
capacitors shown are ceramic. These decoupling capacitors must be placed close to the respective signal pins.
There is a 47Ω source series termination resistor shown on the SDO signal. This resistor must be placed as
close to pin 15 as possible. Series terminations for SCLK and CS must be placed close to the host.
Analog
Supply
Reference
Input
1mF
1mF
C3
C4
Common Analog/
Digital Ground Plane
Input
Signal
Input
Signal
4
5W
470pF
5W
C2
AIN0P
5
AIN0N
6
5W
470pF
5W
C1
AIN1N
7
AIN1P
8
9
3
2
ADS7947
ADS7948
ADS7949
U0
10
11
1
0.1mF
1mF
DVDD C5
C6
16
SDO
15
47W
SCLK
R1
14
CS
13
12
Digital
Supply
Figure 54. Recommended ADC Schematic
Copyright © 2010, Texas Instruments Incorporated
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Product Folder Link(s): ADS7947 ADS7948 ADS7949
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