TPS51220A Datasheet, PDF (28/45 Pages) Texas Instruments – Fixed Frequency, 99% Duty Cycle Peak Current Mode Notebook System Power Controller

TPS51220A
SLUS897 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com
RF[kW]
+
1
ƒ_sw
10⁵
[kHz]
(8)
3. Choose the inductor. The inductance value should be determined to give the ripple current of
approximately 25% to 50% of maximum output current. Recommended ripple current rate is about 30% to
40% at the typical input voltage condition, next equation uses 33%.
L=
1
× ^{(VIN(TYP) - VOUT ) × VOUT}
0.33 x I_OUT(MAX) x f_SW
V_IN(TYP)
(9)
The inductor also needs to have low DCR to achieve good efficiency, as well as enough room above peak
inductor current before saturation.
4. Determine the OCL trip voltage threshold, V_(OCL), and select the sensing resistor.
The OCL trip voltage threshold is determined by TRIP pin setting. To use a larger value improves the S/N
ratio. Determine the sensing resistor using next equation. I_OCL(PEAK) should be approximately 1.5 × I_OUT(MAX)
to 1.7 × I_OUT(MAX).
R_SENSE
+
V_OCL
I_OCL(PEAK)
(10)
5. Determine Rgv. Rgv should be determined from preferable droop compensation value and is given by next
equation based on the typical number of Gmv = 500µS.
Rgv + 0.1
I _OUT(MAX)
I_OCL(PEAK)
V_OUT
1
Gmv Vdroop
(11)
Rgv[kW] + 200
I _OUT(MAX)
I_OCL(PEAK)
V_OUT[V]
Vdroop[mV]
(12)
If no-droop is preferred, attach a series RC network circuit instead of single resistor. Series resistance is
determined using Equation 12 . Series capacitance can be arbitrarily chosen to meet the RC time constant,
but should be kept under 1/10 of f_o. For D-CAP mode, Rgv is used for adjusting ramp compensation. 10kΩ is
a good value to start design with. 6kΩ to 20kΩ can be chosen.
6. Determine output capacitance Co to achieve a stable operation using the next equation. The 0 dB frequency,
f_o, should be kept under 1/3 of the switching frequency.
ƒ₀
+
5
p
I _OCL(PEAK)
1
V_OUT
Gmv Rgv ƒsw
Co ^t 3
(13)
Co
u
15
p
I_OCL(PEAK)
1
V_OUT
Gmv Rgv
ƒsw
(14)
For D-CAP mode, f_o is determined by the output capacitor’s characteristics as below.
ƒ₀ + _2p
1
ESR
ƒsw
Co ^t 3
(15)
Co u _2p
3
ESR
ƒsw
(16)
For better jitter performance, a sufficient amount of feedback signal is required at VFBx pin. The
recommended signal level is approximately 30mV per t_sw (switching period) of the ramping up rate, and more
than 4mV of peak-to-peak voltage.
28
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