TLV320AIC3101 Datasheet, PDF (28/95 Pages) Texas Instruments – LOW-POWER STEREO AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY

TLV320AIC3101
SLAS520C – FEBRUARY 2007 – REVISED JULY 2007
www.ti.com
OVERVIEW (continued)
The sampling rate of the ADC and DAC can be set to f_S(ref)/NCODEC or 2 × f_S(ref)/NCODEC, with NCODEC
being 1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, or 6 for both the NDAC and NADC settings. In the TLV320AIC3101,
NDAC and NADC must be set to the same value, as the device only supports a common sample rate for the
ADC and DAC channels. Therefore NCODEC = NDAC = NADC, and this is programmed by setting the value of
bits D7–D4 equal to the value of bits D3–D0 in register 2, on page 0.
AUDIO CLOCK GENERATION
The audio converters in the TLV320AIC3101 need an internal audio master clock at a frequency of 256 f_S(ref),
which can be obtained in a variety of manners from an external clock signal applied to the device.
A more detailed diagram of the audio clock section of the TLV320AIC3101 is shown in Figure 23.
MCLK BCLK
CLKDIV_CLKIN
PLL_CLKIN
CLKDIV_IN
PLL_IN
Q = 2, 3,….., 16, 17 2/Q
K*R/P
K = J.D
J = 1, 2, 3, ...., 62, 63
D = 0000, 0001, ...., 9998, 9999
R = 1, 2, 3, 4, ...., 15, 16
P = 1, 2, ...., 7, 8
CLKDIV_OUT
PLL_OUT
1/8
PLLDIV_OUT
CODEC_CLKIN
CODEC_CLK = 256 ´ f_S(ref)
CODEC
DAC f_S
ADC f_S
WCLK = f_S(ref)/NCODEC
CODEC f_S = DAC f_S = ADC f_S
Set NCODEC = NADC = NDAC = 1, 1.5, 2, ...., 5.5, 6
DAC DRA => NDAC = 0.5
ADC DRA => NADC = 0.5
Figure 23. Audio Clock Generation Processing
B0153-01
The device can accept an MCLK input from 512 kHz to 50 MHz, which can then be passed through either a
programmable divider or a PLL to get the proper internal audio master clock required by the device. The BCLK
input can also be used to generate the internal audio master clock.
28
Submit Documentation Feedback