LM27403 Datasheet, PDF (28/49 Pages) Texas Instruments – Synchronous Buck Controller with Temperature-Compensated, Inductor-DCR-Based Overcurrent Protection and Programmable Thermal Shutdown

LM27403
SNVS896 A – AUGUST 2013 – REVISED SEPTEMBER 2013
www.ti.com
2. Re-enable soft-start clock to count 5-ms timeout for hiccup delay;
3. At the end of the hiccup delay, re-enter the startup sequence, including the internal enable delay.
Every time a current limit event is detected, the current limit event counter is incremented on the next clock edge.
If the current limit event counter reaches its threshold of five, then the hiccup mode is entered.
NEGATIVE CURRENT LIMIT
Negative current limit detection is in effect only after an overvoltage (OV) condition is met. The OV flag is
deglitched by 10 µs. By the time OV is signaled, the loop has most likely moved into a low- or zero-percent duty
cycle that poses the threat of excessive negative current. Thus, the negative current limit is in effect as soon as
the OV condition is detected rather than waiting for the deglitched version. If the negative current limit is
exceeded, the low-side MOSFET gate (LG pin) is pulled low and the LM27403 enters Negative Current Limit
hiccup mode for 5 ms.
Negative Current Limit hiccup mode (subsequent to OVP) is different from Current Limit hiccup mode in that
zero-cross current detection is active in the latter and the LG output is high. However, as with Current Limit
hiccup mode, the system attempts to restart after the 5-ms timeout, as described in the CURRENT LIMIT
HANDLING section. The LM27403 detects a negative current limit by monitoring the switch-node (SW) voltage
while the low-side MOSFET is on. If the switch-node voltage (that is, the low-side MOSFET drain-source voltage)
rises 100 mV above ground during the low-side MOSFET conduction interval, the comparator trips, signaling that
the negative current limit threshold has been reached. The low-side MOSFET is turned off, thus protecting it from
excess current.
The negative current comparator is valid only when the LG is high. Blanking time lasts 20 ns to 50 ns after LG
has been asserted. Blanking recurs as soon as PWM goes high.
UNDERVOLTAGE THRESHOLD (UVT)
The FB pin is also monitored for an output voltage excursion below the nominal level. However, if the UVT
comparator is tripped, no action occurs on the normal switching cycles. The UVT signal is used solely as a valid
condition for the Power Good flag to transition low. When the FB voltage exceeds 91% of the reference voltage,
the Power Good flag transitions high. Conversely, the Power Good flag transitions low when the FB voltage is
less than 87% of the reference.
OVERVOLTAGE THRESHOLD (OVT)
When the FB voltage exceeds 116.5% of the reference voltage, the Power Good flag transitions low after a 10-µs
deglitch. The control loop attempts to bring the output voltage back to the nominal setpoint. Conversely, when the
FB voltage goes below 113% of the reference, the Power Good flag is allowed to transition high. Negative
current-limit detection is activated when the regulator is in an OV condition. See the NEGATIVE CURRENT
LIMIT section for more details.
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