AFE7070_15 Datasheet, PDF(28/44 Page) Texas Instruments – Dual 14-Bit 65-MSPS Digital-to-Analog Converter With Integrated Analog Quadrature Modulator

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AFE7070_15 Datasheet, PDF (28/44 Pages) Texas Instruments – Dual 14-Bit 65-MSPS Digital-to-Analog Converter With Integrated Analog Quadrature Modulator

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AFE7070

SLOS761D â FEBRUARY 2012 â REVISED JANUARY 2013

DACCLKP

DACCLKN

CLK_IO

(input)

D[13:0]

Identification

IQ_FLAG

SYNC_SLEEP

Dual Input Clock Mode (SDR)

Phase unconstrained (max +/- 4 clk after FIFO sync)

ts th

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Sync

(Initialization)

SYNC_SLEEP

Internal

SYNC

Signal

Internal

Output

Sample

Clock

Internal sync signal based on SYNC_SLEEP low to high, either I or Q

Internal sample clock phase based on IQ_FLAG

Output

waveform

Figure 39. Dual-Input Clock Mode

DUAL-OUTPUT CLOCK MODE

In dual-output clock mode, the user provides a differential DAC clock at pins DACCLKP/N at 2Ã the internal

sample clock frequency. The DACCLK is divided by 2 internally to provide the internal output sample clock, with

the phase determined by the IQ_FLAG input. The IQ_FLAG signal can either be a repetitive high/low signal or a

single event that is used to reset the clock divider phase and identify the I sample.

The AFE7070 outputs a single-ended CMOS-level clock at CLK_IO for latching input data. CLK_IO is an SDR

clock at the input data rate, or 2Ã the internal sample clock frequency. The CLK_IO clock can be used to drive

the input data source (such as digital upconverter) that sends the data to the DAC. Note that the CLK_IO delay

relative to the input DACCLK rising edge (td) in Figure 40) increases with increasing loads.

An external sync can be given on the SYNC_SLEEP pin to reset/initialize internal signal processing blocks.

Because the internal processing blocks process I and Q in parallel, the user can provide the sync signal during

either the I or Q input times (or both).

In the dual-output clock mode, the FIFO is bypassed, so the latency from the data input to the DAC output and

the time from sync input to update of the signal processing block are deterministic.

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