TVP6000C Datasheet, PDF (27/57 Pages) Texas Instruments – NTSC/PAL Digital Video Encoder

SCLK
GLCO
Inactive
MSB
LSB
23-Bit DTO Frequency Control
Inactive Sub Carrier DTO Phase Reset
>128 LLCs 1 LLC
23 LLCs
7 LLCs
1 LLC
Start Bit 0
Where DTO = Discrete Time Oscillator
Figure 2–14. Transmission Timing
2.11 Register Descriptions
The TVP6000 is a standard I²C slave device. All of the registers can be written and read through the I²C
interface. The I²C base addresses of the TVP6000 are dependent on pin 15 (SA) as listed in Table 2–7.
Table 2–7. Base Addresses
PIN 15
0
1
WRITE ADDRESS
(hex)
40
42
READ ADDRESS (hex)
41
43
Table 2–8. Register Bit Allocation Map
REGISTER
R/W
SUB-
ADDRESS
BIT7
BIT6
BIT5
BIT4 BIT3
DEV_ID
R
00
Dev id[7:0]
REV_ID
STATUS
R
01
R
02
Scon Ccon
Rev id[7:0]
Cce
Cco
Reserved
03–39
Reserved
F_CONTROL R/W
3A
Cbar
Fmt2 Y2c
Reserved
3B–59
Reserved
C_PHASE
R/W
5A
Cphase[7:0]
GAIN_U
R/W
5B
Gu[7:0]
GAIN_V
R/W
5C
Gv[7:0]
BLACK_LEVEL R/W
5D
Gu8
Black[6:0]
BLANK_LEVEL R/W
5E
Gv8
GAIN_Y
R/W
5F
Blank[6:0]
Gy[7:0]
X_COLOR
R/W
60
0
Xc
Gy8
M_CONTROL R/W
61
Sdown Cdown Palphs
0
Glce
BSTAMP
R/W
62
Sqp
Bstap[6:0]
S_CARR1
R/W
63
Fsc[7:0]
S_CARR2
R/W
64
Fsc[15:8]
S_CARR3
R/W
65
Fsc[23:16]
S_CARR4
R/W
66
Fsc[31:24]
LINE21_O0
R/W
67
LINE21_O1
R/W
68
L21o[7:0]
L21o[15:8]
BIT2
Uv2c
Cbw
BIT1 BIT0
Fsq[2:0]
Fmt[1:0]
Lcd[2:0]
Pal
Ffrq
2–15