TPS23754_10 Datasheet, PDF (27/41 Pages) Texas Instruments – High Power/High Efficiency PoE Interface and DC/DC Controller

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TPS23754
TPS23754-1
TPS23756
SLVS885D – OCTOBER 2008 – REVISED DECEMBER 2009
APD Pin Divider Network, R_APD1, R_APD2
The APD pin can be used to disable the TPS23754 internal hotswap MOSFET giving the adapter source priority
over the PoE source. An example calculation is provided, see literature number SLVA306A.
PPD Pin Divider Network, R_PPD1, R_PPD2
The PPD pin can be used to override the internal hotswap MOSFET UVLO (V_{UVLO_R} and V_{UVLO_H}) when using
low voltage adapters connected between V_DD and V_SS. The PPD pin has an internal 5 μA pulldown current
source. As an example, consider the choice of R_PPD1 and R_PPD2, for a 24 V adapter.
1. Select the startup voltage, V_ADPTR-ON approximately 75% of nominal for a 24 V adapter. Assuming that the
adapter output is 24 V ± 10%, this provides 15% margin below the minimum adapter operating voltage.
2. Choose V_ADPTR-ON = 24 V × 0.75 = 18 V
3. Choose R_PPD2 = 3.01 kΩ
4. Calculate R_PPD1
æ
R_PPD1
=
ç
ç
ç
ç
V_{AD PT R_ ON}
V_{PPD EN}
(a)
è
R_PPD2
-
-
V_{PPD EN}
I_PPD
ö
÷
÷
÷
÷
ø
=
æ
ç
ç
èçç
18 V - 1.55 V
1.55 V
3.01 kW
-
5
mA
ö
÷
÷
ø÷÷
=
32.26
kW
(b) Choose R_PPD1 = 32.4 kΩ
5. Check PPD turn on and PPD turn off voltages
(a)
é
V_{ADPTR_ON} = V_PPDEN + êêëR_PPD1
´
æ
ç
V_PPDEN
è ^RPPD2
öù
-
I_PPD
÷ú
øúû
= 18.07 V
( ) ^{( )} V_{ADPTR_OFF} =
(b)
V_PPDEN
-
V_PPDH
é
+ _êëêR_PPD1
´
æ
èçç
V_PPDEN - V_PPDH
R_PPD2
öù
- I_PPD ÷÷øúûú = 14.54 V
(c) Voltages look acceptable.
6. Check PPD resistor power consumption.
(a)
P_RPPD
=
(V_DD - V_SS )²
R_PPD1 + R_PPD2
(24 V ´ 1.1)²
=
= 19.6 mW
3.01 kW + 32.4 kW
(b) Power is acceptable, but resistor values could be increased to reduce the power loss.
Setting Frequency (R_FRS) and Synchronization
The converter switching frequency is set by connecting R_FRS from the FRS pin to ARTN. The frequency may be
set as high as 1 MHz with some loss in programming accuracy as well as converter efficiency. Synchronization
at high duty cycles may become more difficult above 500 kHz due to the internal oscillator delays reducing the
available on-time. As an example:
1. Assume a desired switching frequency (f_SW) of 250 kHz.
2. Compute R_FRS:
(a)
R_FRS (k W) =
17250
f_SW (kHz)
=
17250
250
= 69
(b) Select 69.8 kΩ.
The TPS23754 may be synchronized to an external clock to eliminate beat frequencies from a sampled system,
or to place emission spectrum away from an RF input frequency. Synchronization may be accomplished by
applying a short pulse (T_SYNC) of magnitude V_SYNC to FRS as shown in Figure 30. R_FRS should be chosen so that
the maximum free-running frequency is just below the desired synchronization frequency. The synchronization
pulse terminates the potential on-time period, and the off-time period does not begin until the pulse terminates.
The pulse at the FRS pin should reach between 2.5 V and V_B, with a minimum width of 22 ns (above 2.5 V) and
rise/fall times less than 10 ns. The FRS node should be protected from noise because it is high-impedance. An
R_T on the order of 100 Ω in the isolated example reduces noise sensitivity and jitter.
Copyright © 2008–2009, Texas Instruments Incorporated
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