TAS5424C-Q1_15 Datasheet, PDF (27/51 Pages) Texas Instruments – TAS54x4C-Q1 Four-Channel Automotive Digital Amplifiers

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TAS5414C-Q1, TAS5424C-Q1
SLOS795E – SEPTEMBER 2013 – REVISED JANUARY 2015
Programming (continued)
7.5.3 Random Read
As shown in Figure 19, a random read or single-byte read transfer begins with the master device transmitting a
start condition followed by the I²C device address and the read/write bit. For the single-byte read transfer, the
master device transmits both a write followed by a read. Initially, a write transfers the address byte or bytes of
the internal memory address to be read. Thus, the read/write bit is a 0. After receiving the address and the
read/write bit, the TAS5414C-Q1 or TAS5424C-Q1 responds with an acknowledge bit. In addition, after sending
the internal memory address byte or bytes, the master device transmits another start condition followed by the
device address and the read/write bit again. This time the read/write bit is a 1, indicating a read transfer. After
receiving the address and the read/write bit, the device again responds with an acknowledge bit. Next, the
TAS5414C-Q1 or TAS5424C-Q1 transmits the data byte from the memory address being read. After receiving
the data byte, the master device transmits a not-acknowledge followed by a stop condition to complete the
single-byte read transfer.
Start
Condition
Acknowledge
Repeat Start
Condition
Acknowledge
Acknowledge
Not
Acknowledge
A6 A5
A1 A0 R/W ACK A7 A6 A5 A4
A0 ACK
A6 A5
A1 A0 R/W ACK D7 D6
D1 D0 ACK
I²C Device Address and
Read/Write Bit
Subaddress
I²C Device Address and
Read/Write Bit
Figure 19. Random Read Transfer
Data Byte
Stop
Condition
T0036-03
7.5.4 Sequential Read
A sequential read transfer is identical to a single-byte read transfer except for the transmission of multiple data
bytes by the TAS5414C-Q1 or TAS5424C-Q1 to the master device as shown in Figure 20. Except for the last
data byte, the master device responds with an acknowledge bit after receiving each data byte and automatically
increments the I²C subaddress by one. After receiving the last data byte, the master device transmits a not-
acknowledge followed by a stop condition to complete the transfer.
Start
Condition
Acknowledge
Repeat Start
Condition
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Not
Acknowledge
A6
A0 R/W ACK A7 A6 A5
A0 ACK
A6 A0 R/W ACK D7
D0 ACK D7
D0 ACK D7
D0 ACK
I²C Device Address and
Read/Write Bit
Subaddress
I²C Device Address and First Data Byte
Read/Write Bit
Other Data Bytes
Last Data Byte
Figure 20. Sequential Read Transfer
Stop
Condition
T0036-04
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