ADS8331 Datasheet, PDF (27/39 Pages) Texas Instruments – Low-Power, 16-Bit, 500kSPS, 4-/8-Channel Unipolar Input ANALOG-TO-DIGITAL CONVERTERS with Serial Interface

ADS8331
ADS8332
www.ti.com
SBAS363 – DECEMBER 2009
DIGITAL INTERFACE
The serial interface is designed to accommodate the latest high-speed processors with an SCLK frequency of up
to 40MHz (VA = VBD = 5.0V). Each cycle starts with the falling edge of FS/CS. The internal data register
content, which is made available to the output register at the end of conversion, is presented on the SDO output
pin on the falling edge of FS/CS. The first bit is the most significant bit (MSB). The output data bits are valid on
the falling edge of SCLK with the t_D2 delay (see the Timing Characteristics)so that the host processor can read
the data on the falling edge. Serial data input is also read on the falling edge of SCLK.
The complete serial I/O cycle starts after the falling edge of FS/CS and ends 16 falling edges of SCLK later (see
NOTE). The serial interface works with CPOL = '1', CPHA = '0'. This setting means the falling edge of FS/CS
may fall while SCLK is high. The same timing relaxation applies to the rising edge of FS/CS where SCLK may be
high or low as long as the last SCLK falling edge happens before the rising edge of FS/CS.
NOTE
There are cases where a cycle can be anywhere from 4 SCLKs up to 24 SCLKs,
depending on the read mode combination. See Table 4 for details.
Internal Register
The internal register consists of two parts: four bits for the Command register (CMR) and 12 bits for the
Configuration register (CFR).
Table 4. Command Set Defined by Command Register (CMR)⁽¹⁾
D[15:12]
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
HEX
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
COMMAND
Select analog input channel 0
Select analog input channel 1
Select analog input channel 2
Select analog input channel 3
Select analog input channel 4⁽²⁾
Select analog input channel 5⁽²⁾
Select analog input channel 6⁽²⁾
Select analog input channel 7⁽²⁾
Reserved
Reserved
Reserved
Wake up
Read CFR
Read data
Write CFR
Default mode
(load CFR with default value)
D[11:0]
WAKE UP
MINIMUM
FROM
SCLKs
AUTO-NAP
REQUIRED
R/W
Don't care
Y
4
W
Don't care
Y
4
W
Don't care
Y
4
W
Don't care
Y
4
W
Don't care
Y
4
W
Don't care
Y
4
W
Don't care
Y
4
W
Don't care
Y
4
W
Reserved
—
—
—
Reserved
—
—
—
Reserved
—
—
—
Don't care
Y
4
W
Don't care
—
16
R
Don't care
—
16
R
CFR Value
—
16
W
Don't care
Y
4
W
(1) The first four bits from SDO after the falling edge of FS/CS are the four MSBs from the previous conversion result. The next 12 bits from
SDO are the contents of the CFR.
(2) These commands apply only to the ADS8332; they are reserved (not availble) for the ADS8331.
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): ADS8331 ADS8332
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