TPS40050-Q1_15 Datasheet, PDF (26/35 Pages) Texas Instruments – WIDE-INPUT SYNCHRONOUS BUCK CONTROLLER

TPS40050ĆQ1
TPS40051ĆQ1
TPS40053ĆQ1
SGLS219A − NOVEMBER 2003 − REVISED MAY 2008
DESIGN EXAMPLE
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6. Calculate the inductor value
The inductor value is calculated from equation (6).
L
+
(24
24 V
* 3.3
3.2
V)
A
3.3 V
300 kHz
+
2.96
mH
(61)
A 2.9-µH Coev DXM1306−2R9 or 2.6-µH Panasonic ETQ−P6F2R9LFA can be used.
7. Setting the switching frequency
The clock frequency is set with a resistor (R_T) from the RT pin to ground. The value of R_T can be found from
equation (1), with f_SW in kHz.
ǒ Ǔ R_T + _fSW
1
17.82
10^{*6 * 23 kW + 164 kW N use 165 kW}
(62)
8. Programming the ramp generator circuit
The PWM ramp is programmed through a resistor (R_KFF) from the KFF pin to V_IN. The ramp generator also
controls the input UVLO voltage. For an undervoltage level of 10 V, R_KFF can be calculated from (2)
ǒ Ǔ _{RKFF + VIN(min) * 3.5} ǒ_{58.14 RT ) 1340}Ǔ _{kW + 71 kW N use 71.5 kW}
(63)
9. Calculating the output capacitance (C_O)
In this example the output capacitance is determined by the load response requirement of ∆V = 0.3 V for a 1 A
to 8 A step load. C_O can be calculated using (12)
ǒ Ǔ 2.9 m (8 A)² * (1 A)²
C_O +
ǒ Ǔ (3.3)² _* (3.0)²
+ 97 mF
(64)
Using (7) we can calculate the ESR required to meet the output ripple requirements.
ǒ Ǔ 33 mV + 3.2 A ESR ) ₈
1
73 mF 300 kHz
(65)
ESR + 10.3 mW * 3.33 mW + 6.97 mW
(66)
For this design example two (2) Panasonic SP EEFUEOJ1B1R capacitors, (6.3 V, 180 µF, 12 mΩ) are used.
10. Calculate the soft-start capacitor (C_SS)
This design requires a soft−start time (t_START) of 1 ms. C_SS can be calculated on (14)
C_SS
+
2.3 mA
0.7 V
1 ms + 3.29 nF + 3300 pF
(67)
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