SN74LVC125A_07 Datasheet, PDF (26/46 Pages) Texas Instruments – QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

MSP430C11x1, MSP430F11x1A
MIXED SIGNAL MICROCONTROLLER
SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
input/output schematic
Port P1, P1.0 to P1.3, input/output with Schmitt-trigger
P1SEL.x
P1DIR.x
Direction Control
From Module
P1OUT.x
Module X OUT
0
1
0
Pad Logic
1
VCC
(See Note 1)
(See Note 2)
P1.0 − P1.3
(See Note 2)
P1IN.x
EN
Module X IN
D
(See Note 1)
GND
P1IRQ.x
P1IE.x
EN
Q
P1IFG.x
Set
Interrupt
Edge
Select
NOTE: x = Bit/identifier, 0 to 3 for port P1
Interrupt
Flag
P1IES.x
P1SEL.x
PnSel.x PnDIR.x
Direction
control from
module
PnOUT.x Module X OUT PnIN.x
Module X IN
PnIE.x
PnIFG.x
P1Sel.0 P1DIR.0
P1Sel.1 P1DIR.1
P1DIR.0
P1DIR.1
P1OUT.0
P1OUT.1
VSS
Out0 signal†
P1IN.0
P1IN.1
TACLK†
CCI0A†
P1IE.0
P1IE.1
P1IFG.0
P1IFG.1
P1Sel.2 P1DIR.2
P1DIR.2
P1OUT.2 Out1 signal† P1IN.2
CCI1A†
P1IE.2
P1IFG.2
P1Sel.3 P1DIR.3
P1DIR.3
P1OUT.3 Out2 signal† P1IN.3
CCI2A†
P1IE.3
P1IFG.3
† _{Signal from or to Timer_A}
NOTES: 1. Optional selection of pullup or pulldown resistors with ROM (masked) versions
2. Fuses for optional pullup and pulldown resistors can only be programmed at the factory (ROM versions only).
PnIES.x
P1IES.0
P1IES.1
P1IES.2
P1IES.3
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