66AK2E05_15 Datasheet, PDF (259/282 Pages) Texas Instruments – 66AK2E0x Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

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66AK2E05, 66AK2E02
SPRS865D – NOVEMBER 2012 – REVISED MARCH 2015
11.18 SGMII/XFI Management Data Input/Output (MDIO)
The management data input/output (MDIO) module implements the 802.3 serial management interface to
interrogate and control up to 32 Ethernet PHY(s) connected to the device, using a shared two-wire bus.
Application software uses the MDIO module to configure the auto-negotiation parameters of each PHY
attached to the EMAC, retrieve the negotiation results, and configure required parameters in the gigabit
Ethernet (GbE) and 10-gigabit Ethernet (10GbE) switch subsystems for correct operation. The module
allows almost transparent operation of the MDIO interface, with very little attention from the SoC. For more
information, see the Gigabit Ethernet (GbE) Switch Subsystem (1 GB) User's Guide (SPRUGV9) and the
KeyStone II Architecture 10 Gigabit Ethernet Subsystem User's Guide (SPRUHJ5).
(see Figure 11-46)
NO.
1 tc(MDCLK)
2 tw(MDCLKH)
3 tw(MDCLKL)
4 tsu(MDIO-MDCLKH)
5 th(MDCLKH-MDIO)
tt(MDCLK)
Table 11-48. MDIO Timing Requirements
Cycle time, MDCLK
Pulse duration, MDCLK high
Pulse duration, MDCLK low
Setup time, MDIO data input valid before MDCLK high
Hold time, MDIO data input valid after MDCLK high
Transition time, MDCLK
MIN
MAX UNIT
400
ns
180
ns
180
ns
10
ns
10
ns
5
ns
1
MDCLK
MDIO
(Input)
2
3
4
5
Figure 11-46. MDIO Input Timing
Table 11-49. MDIO Switching Characteristics
(see Figure 11-47)
NO.
PARAMETER
MIN
6
td(MDCLKH-MDIO) Delay time, MDCLK high to MDIO data output valid
10
7
th(MDCLKH-MDIO) Hold time, MDIO data output valid after MDCLK high
10
8
td(MDCLKH-MDIO) Delay time, MDCLK high to MDIO Hi-Z
10
MAX
300
300
UNIT
ns
ns
ns
MDCLK
MDIO
(Ouput)
1
7
7
6
8
Figure 11-47. MDIO Output Timing
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66AK2E0x Peripheral Information and Electrical Specifications 259
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