TSB41LV04A Datasheet, PDF (25/49 Pages) Texas Instruments – IEEE 1394a FOUR-PORT CABLE TRANSCEIVER/ARBITER

TSB41LV04A
IEEE 1394a FOUR-PORT CABLE TRANSCEIVER/ARBITER
APPLICATION INFORMATION
SLLS379 – OCTOBER 1999
using the TSB41LV04A with a non-P1394a link layer (continued)
The P1394a Supplement includes enhancements to the Annex J interface that must be comprehended when
using the TSB41LV04A with a non-P1394a LLC device.
D A new LLC service request was added, which allows the LLC to temporarily enable and disable
asynchronous arbitration accelerations. If the LLC does not implement this new service request, the
arbitration enhancements should not be enabled (see the EAA bit in PHY register 5).
D The capability to perform multispeed concatenation (the concatenation of packets of differing speeds) was
added in order to improve bus efficiency (primarily during isochronous transmission). If the LLC does not
support multispeed concatenation, multispeed concatenation should not be enabled in the PHY (see the
EMC bit in PHY register 5).
D In order to accommodate the higher transmission speeds expected in future revisions of the standard,
P1394A extended the speed code in bus requests from 2 bits to 3 bits, increasing the length of the bus
request from 7 bits to 8 bits. The new speed codes were carefully selected so that new P1394a PHY and
LLC devices would be compatible, for speeds from S100 to S400, with legacy PHY and LLC devices that
use the 2-bit speed codes. The TSB41LV04A will correctly interpret both 7-bit bus requests (with 2-bit speed
codes) and 8-bit bus requests (with 3-bit speed codes). Moreover, if a 7-bit bus request is immediately
followed by another request (e.g., a register read or write request), the TSB41LV04A will correctly interpret
both requests. Although the TSB41LV04A will correctly interpret 8-bit bus requests, a request with a speed
code exceeding S400 will result in the TSB41LV04A transmitting a null packet (data-prefix followed by
data-end, with no data in the packet).
More explanation is included in the TI application note IEEE 1394a Features Supported by TI TSB41LV0X
Physical Layer Devices, TI literature number SLL019.
using the TSB41LV04A with a lower-speed link layer
Although the TSB41LV04A is an S400 capable PHY, it may be used with lower speed LLCs, such as the S200
capable TSB12LV31. In such a case, the LLC has fewer data terminals than the PHY, and some Dn terminals
on the TSB41LV04A will be unused. Unused Dn terminals should be pulled to ground through 10-kΩ resistors.
The TSB41LV04A transfers all received packet data to the LLC, even if the speed of the packet exceeds the
capability of the LLC to accept it. Some lower speed LLC designs do not properly ignore packet data in such
cases. On the rare occasions that the first 16 bits of partial data accepted by such a LLC match a node’s bus
and node ID, spurious header CRC or tcode errors may result.
During bus initialization following a bus-reset, each PHY transmits a self-ID packet that indicates, among other
information, the speed capability of the PHY. The bus manager (if one exists) builds a speed-map from the
collected self-ID packets. This speed-map gives the highest possible speed that can be used on the
node-to-node communication paths between every pair of nodes in the network.
In the case of a node consisting of a higher-speed PHY and a lower-speed LLC, the speed capability of the node
(PHY and LLC in combination) is that of the lower-speed LLC. A sophisticated bus manager may be able to
determine the LLC speed capability by reading the configuration ROM Bus_Info_Block, or by sending
asynchronous request packets at different speeds to the node and checking for an acknowledge; the
speed-map may then be adjusted accordingly. The speed-map should reflect that communication to such a
node must be done at the lower speed of the LLC, instead of the higher speed of the PHY. However, speed-map
entries for paths that merely pass through the node’s PHY, but do not terminate at that node, should not be
restricted by the lower speed of the LLC.
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