TSB12LV23 Datasheet, PDF (25/85 Pages) Texas Instruments – TSB12LV23 OHCI-Lynx PCI-Based IEEE 1394 Host Controller

3.16 MIN_GNT and MAX_LAT Register
The MIN_GNT and MAX_LAT register is used to communicate to the system the desired setting of the latency timer
register (see Section 3.7). If a serial ROM is detected, then the contents of this register are loaded through the serial
ROM interface after a PCI reset. If no serial ROM is detected, then this register returns a default value that
corresponds to the MIN_GNT = 2, MAX_LAT = 4.
Bit
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Name
MIN_GNT and MAX_LAT
Type
RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU
Default 0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
BIT
15–8
7–0
Register:
Type:
Offset:
Default:
FIELD NAME
MAX_LAT
MIN_GNT
MIN_GNT and MAX_LAT
Read/Update
3Eh
0202h
Table 3–13. MIN_GNT and MAX_LAT Register Description
TYPE
RU
RU
DESCRIPTION
Maximum latency. The contents of this register may be used by host BIOS to assign an arbitration
priority-level to the TSB12LV23. The default for this register indicates that the TSB12LV23 may need to
access the PCI bus as often as every 0.25 µs; thus, an extremely high priority level is requested. The
contents of this field may also be loaded through the serial ROM.
Minimum grant. The contents of this register may be used by host BIOS to assign a latency timer register
value to the TSB12LV23. The default for this register indicates that the TSB12LV23 may need to sustain
burst transfers for nearly 64 µs; thus, requesting a large value be programmed in the TSB12LV23 latency
timer register (see Section 3.7).
3.17 PCI OHCI Control Register
The PCI OHCI control register is defined by the 1394 Open Host Controller Interface Specification and provides a
bit for big endian PCI support.
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
PCI OHCI control
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Name
PCI OHCI control
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R R/W
Default 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
31–1
0
Register:
Type:
Offset:
Default:
PCI OHCI control
Read/Write
40h
0000 0000h
FIELD NAME
RSVD
GLOBAL_SWAP
Table 3–14. PCI OHCI Control Register Description
TYPE
R
R/W
DESCRIPTION
Reserved. Bits 31–1 return 0s when read.
When this bit is set, all quadlets read from and written to the PCI interface are byte swapped (big
endian).
3–11