TAS5717 Datasheet, PDF (25/67 Pages) Texas Instruments – 10-W/15-W Digital Audio Power Amplifier with Integrated Cap-Free HP Amplifier

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2-Channel Left-Justified Stereo Input
LRCLK
16 Clks
Left Channel
SCLK
TAS5717
TAS5719
SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011
SCLK
16 Clks
Right Channel
MSB
16-Bit Mode
15 14 13 12 11 10 9 8
LSB MSB
5 4 3 2 1 0 15 14 13 12 11 10 9 8
NOTE: All data presented in 2s-complement form with MSB first.
Figure 31. Left-Justified 32-f_S Format
LSB
5432 10
T0266-02
Right-Justified
Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when
it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at
32, 48, or 64 × f_S is used to clock in the data. The first bit of data appears on the data 8 bit-clock periods (for
24-bit data) after LRCLK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before
LRCLK transitions. The data is written MSB-first and is valid on the rising edge of bit clock. The DAP masks
unused leading data-bit positions.
2-Channel Right-Justified (Sony Format) Stereo Input
LRCLK
32 Clks
Left Channel
32 Clks
Right Channel
SCLK
SCLK
MSB
24-Bit Mode
20-Bit Mode
16-Bit Mode
23 22
19 18
19 18
15 14
15 14
15 14
LSB MSB
10
10
10
23 22
19 18
15 14
19 18
15 14
15 14
Figure 32. Right-Justified 64-f_S Format
LSB
10
10
10
T0034-03
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Product Folder Link(s): TAS5717 TAS5719
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