ADS8881 Datasheet, PDF (25/44 Pages) Texas Instruments – 18-Bit, 1-MSPS, Serial Interface, microPower, Miniature, True-Differential Input, SAR Analog-to-Digital Converter

ADS8881
www.ti.com
SBAS547A – MAY 2013 – REVISED JULY 2013
4-Wire CS Mode With a Busy Indicator
This interface option is most useful when a single ADC is connected to an SPI-compatible digital host and an
interrupt-driven data transfer is desired. In this interface option, the analog sample is least affected by clock jitter
because the CONVST signal (used to sample the input) is independent of the data read operation. In this
interface option, DIN is controlled by the digital host and functions as CS (as shown in Figure 57). The pull-up
resistor on the DOUT pin ensures that the IRQ pin of the digital host is held high when DOUT goes to 3-state. As
shown in Figure 58, when DIN is high, a CONVST rising edge selects CS mode, forces DOUT to 3-state,
samples the input signal, and causes the device to enter a conversion phase. In this interface option, CONVST
must be held high from the start of the conversion until all data bits are read. Conversion is done with the internal
clock and continues regardless of the state of DIN. As a result, DIN (acting as CS) can be pulled low to select
other devices on the board. However, DIN must be pulled low before the minimum conversion time (t_conv-min)
elapses and remains low until the maximum possible conversion time (t_conv-max) elapses. A low level on the DIN
input at the end of a conversion ensures the device generates a busy indicator.
DIN _CONVST
SCLK
DVDD
CS
CNV
CLK
DOUT
SDI
ADC
IRQ
Digital Host
Figure 57. Connection Diagram: 4-Wire CS Mode With a Busy Indicator
CONVST
t_conv-min
t_conv-max
1/f_sample
t_ACQ
DIN
SCLK
DOUT
SDO Pulled-up
DIN =0
œœ
1
2
3 17
18
19
BUSY
œœ
D17 D16 D2
D1
D0
œœ
ADC Acquiring
STATE ^{Sample N}
Converting
Sample N
Conversion Result of Sample N Clocked-out
while Acquiring Sample N+1
Figure 58. Interface Timing Diagram: 4-Wire CS Mode With a Busy Indicator
When conversion is complete, the device enters an acquisition phase and powers down, DOUT comes out of 3-
state, and the device outputs a busy indicator bit (low level) on the DOUT pin. This configuration provides a high-
to-low transition on the IRQ pin of the digital host. The data bits are clocked out, MSB first, on the subsequent
SCLK falling edges. Data are valid on both SCLK edges. Data are valid on both edges of SCLK and can be
captured on either edge. However, a digital host capturing data on the SCLK falling edge can achieve a faster
reading rate (provided t_{h_CK_DO} is acceptable). DOUT goes to 3-state after the 19th SCLK falling edge or when
DIN goes high, whichever occurs first.
Care must be taken so that CONVST and DIN are not both low together at any time during the cycle.
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: ADS8881
Submit Documentation Feedback
25