TPS40195 Datasheet, PDF (24/39 Pages) Texas Instruments – 4.5-V TO 20-V SYNCHRONOUS BUCK CONTROLLER WITH SYNCHRONIZATION AND POWER GOOD

TPS40195
SLUS720 – FEBRUARY 2007
www.ti.com
Using the parameters from its data sheet the actual expected power losses were calculated. Conduction loss is
0.394 W, body diode loss is 0.210 W and the gate loss was 0.063 W. This totals 0.667 W associated with the
rectifier MOSFET.
The ratio between C_gs and C_gd should be greater than one. The Si7886 capacitor meets this criterion and helps
reduce the risk of dv/dt induced turn on of the rectifier MOSFET. If this is likely to be a problem a small resistor
may be added in series with the boost capacitor, C_BOOST. to slow the turn on speed of Q_SW at the expense of
increased switching losses in that device.
Component Selection for the TPS40195
Timing Resistor, R_T
The timing resistor is calculated using the following equation.
R_T
=
2.5 ´ (10)⁷
f_S
=
2.5
´
(10
7
)
300
=
83.3 kW
(24)
A standard value resistor of 82.5 kΩ is used.
Setting UVLO
The equations below are used to set the UVLO voltages.
R_UVLO1 =
V_ON - V_OFF
I_UVLO
=
7-6
5.2 ´ (10)^-6
= 192.3kW
(25)
R_UVLO2
= R_UVLO1 ´
V_UVLO
(V_ON - V_UVLO )
= 192.3kW ´
1.26
7 - 1.26
=
42.2kW
(26)
The UVLO threshold voltage ( V_UVLO) is 1.26 V. The module has a turn on voltage of 7 V and a turn off voltage
of 6 V. This sets R_UVLO1to 191 kΩ, the nearest standard value. The second resistor R_UVLO2 is 42.2 kΩ.
Setting the Soft-Start Time
The selection of the soft start time should be greater than the time constant of the output filter, L_OUT and C_OUT.
This time is given in Equation 27 and Equation 28.
t_START ³ 2p ´ L_OUT ´ C_OUT
(27)
t_START ³ 6.28 ´ 2.5 ´ (10)^-6 ´ 300 ´ (10)^-6 = 0.172ms
(28)
The soft-start time is determined using Equation 29 . The TPS40195 uses a counter operating at the clock
frequency that increments an internal DAC until it reaches the turn on threshold voltage of 0.591 V. The number
of counts required to reach this threshold is determined by one of three settings on the SS pin. In this case, the
pin is floating (with a small bypass capacitor) which sets the clock count (N_DAC) to 1024 and the soft-start time is
2.0 ms
t_SS
= 0.591´ ^NDAC
f_SW
= 0.591´ ¹⁰²⁴
300
= 2.0 ms
(29)
24
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