TMS320LC549 Datasheet, PDF (24/61 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR

TMS320LC549
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS077B – SEPTEMBER 1998 – REVISED FEBRUARY 2000
memory and parallel I/O interface timing (continued)
switching characteristics over recommended operating conditions for a parallel I/O port read
(IOSTRB = 0)^†‡ (see Figure 7)
PARAMETER
td(CLKL-A)
Delay time, address valid from CLKOUT low
td(CLKH-ISTRBL) Delay time, IOSTRB low from CLKOUT high
td(CLKH-ISTRBH) Delay time, IOSTRB high from CLKOUT high
th(A)IOR
Hold time, address after CLKOUT low
† _{Address and IS timings are included in timings referenced as address.}
‡ _{See Table 1, Table 2, and Table 3 for address bus timing variation with load capacitance.}
’549-66
MIN MAX
–1
6
0
5
–1
6
–1
6
’549-80
MIN MAX
–1
6
0
5
–1
6
–1
6
UNIT
ns
ns
ns
ns
24
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