THS1007 Datasheet, PDF (24/36 Pages) Texas Instruments – 10-BIT, 4 ANALOG INPUT, 6-MSPS, SIMULATANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

THS1007
SLAS286A – AUGUST 2000– REVISED DECEMBER 2002
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Test Mode
The test mode of the ADC is selected via bit 8 and bit 9 of control register 0. The different selections are shown
in Table 10.
Table 10. Test Mode
BIT 9
TEST1
0
0
1
1
BIT 8
TEST0
0
1
0
1
OUTPUT RESULT
Normal mode
VREFP
((VREFM)+(VREFP))/2
VREFM
Three different options can be selected. This feature allows support testing of hardware connections between
the ADC and the processor.
Control Register 1, Write Only (see Table 7)
BIT 11 BIT10
BIT 9
BIT 8
0
1
RESERVED OFFSET
BIT 7
BIN/2s
BIT 6
R/W
BIT 5
RES
BIT 4
RES
BIT 3
RES
BIT 2
RES
BIT 1
SRST
BIT 0
RESET
Table 11. Control Register 1 Bit Functions
BITS
0
1
2, 3
4
5
6
7
8
9
RESET
VALUE
0
0
0,0
1
1
0
0
0
0
NAME
FUNCTION
RESET
Reset
Writing a 1 into this bit resets the device and sets the control register 0 and control register 1 to the reset values.
To bring the device out of RESET, a 0 has to be written into this bit.
SRST
Writing a 1 into this bit resets the sync generator. When running in multichannel mode, this must be set during the
configuration cycle.
RES
Reserved
RES
Reserved
RES
Reserved
R/W
R/W, RD/WR selection
Bit 6 of control register 1 controls the function of the inputs RD and WR. When bit 6 in control register 1 is set to
1, WR becomes a R/W input and RD is disabled. From now on a read is signalled with R/W high and a write with
R/W as a low signal. If bit 6 in control register 1 is set to 0, the input RD becomes a read input and the input WR
becomes a write input.
BIN/2s
Complement select
If bit 7 of control register 1 is set to 0, the output value of the ADC is in twos complement. If bit 7 of
control register 1 is set to 1, the output value of the ADC is in binary format. Refer to Table 2 through Table 5.
OFFSET
Offset cancellation mode
Bit 8 = 0 → normal conversion mode
Bit 8 = 1 → offset calibration mode
If a 1 is written into bit 8 of control register 1, the device internally sets the inputs to zero and does a conver-
sion. The conversion result is stored in an offset register and subtracted from all conversions in order to
reduce the offset error.
RESERVED Always write 0.
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