TAS3001C Datasheet, PDF (24/56 Pages) Texas Instruments – Stereo Audio Digital Equalizer

3.2.5 I²C Serial Port Timing
PARAMETER
MIN MAX UNIT
f(scl)
SCL clock frequency
0 100 kHz
tBUF
Bus free time between start and stop
4.7
µs
tw(low)
Pulse duration, SCL clock low (see Note 1)
4.7
µs
tw(high)
Pulse duration, SCL clock high (see Note 2)
4
µs
th(STA)
Hold time, repeated start
4
µs
tsu(STA)
th(DAT)
Setup time, repeated start
Hold time, data
4.7
20 µs
0†
µs
tsu(DAT) Setup time, data
250
ns
tr
Rise time for SDA and SCL
1000 ns
tf
Fall time for SDA and SCL
300 ns
tsu(STO) Setup time for stop condition
4
µs
† _{A device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL.}
NOTES: 1. tw(low) is measured from the end of tf to the beginning of tr.
2. tw(high) is measured from the end of tr to the beginning of tf.
PS
P
SDA
tBUF
SCL
Valid
th(STA)
tr
th(DAT)
tsu(DAT)
Change of Data ^tf
Allowed
th(STA)
tsu(STA)
Data Line
Stable
Figure 3−4. I²C Serial Port Timing
tsu(STO)
3−4