SN74V215_08 Datasheet, PDF (24/43 Pages) Texas Instruments – 512 X 18, 1024 X 18, 2048 X 18, 4096 X 18 DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES

WCLK
1
1
tENS
WEN
tDS
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎÎÎÎÎ _D0–D17
W1
tDH
W2
W3
W4
tDS
tDS
tDS
tENH
W[n+2]
W[n+3]
W[n+4]
W
D – 1+ ₁
2
W
D – 1+ ₂
2
W
D – 1+ ₃
2
W[D-m-2]
W[D-m-1]
W[D-m] W[D-m+1] W[D-m+2]
W[D]
W[D+1]
tSKEW1
tSKEW2 (see Note B)
RCLK
1
2
3
REN
Q0–Q17
Data in Output Register
OR
PAE
HF
PAF
IR
tA
tREF
tPAES
W1
tHF
tPAFS
tWFF
NOTES: A. t _SKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for OR to go low after two RCLK cycles plus tREF . If the time between the rising
edge of WLCK and the rising edge of RCLK is less than t _SKEW1, the OR deassertion might be delayed one extra RCLK cycle.
B. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to go high during the current clock cycle. If the time between the rising edge
of WCLK and the rising edge of RCLK is less than tSKEW2, the PAE deassertion might be delayed one extra RCLK cycle.
C. LD is high, OE is low.
D. n = PAE offset, m = PAF offset, D = maximum FIFO depth = 513 words for the SN74V215, 1025 words for the SN74V225, 2049 words for the SN74V235, and 4097 words
for the SN74V245.
E. Select synchronous FWFT mode by setting ( FL , RXI , WXI ) = (1,0,1) during reset.
Figure 16. Write Timing With Synchronous Programmable Flags (FWFT Mode)