ADS5474-SP Datasheet, PDF (24/28 Pages) Texas Instruments – Class V, 14-BIT, 400-MSPS ANALOG-TO-DIGITAL CONVERTER

ADS5474-SP
SLAS574A – SEPTEMBER 2013 – REVISED DECEMBER 2013
Low-Jitter Clock Distribution
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Board Master
Reference Clock
(high or low jitter)
10 MHz
REF
LVPECL
400 MHz
CLKIN
CLKIN
ADC
Low-Jitter Oscillator
800 MHz
VCXO
LVPECL
or
LVCMOS
CDC
(Clock Distribution Chip)
800 MHz (to transmit DAC)
100 MHz (to DSP)
200 MHz (to FPGA)
To Other
ADS5474-SP
CDCM7005-SP
This is an example block diagram.
Consult the CDCM7005 data sheet for proper schematic and specifications regarding allowable input and output
frequency and amplitude ranges.
Figure 38. Acceptable Jitter Clock Circuit
Digital Outputs
The ADC provides 14 LVDS-compatible, offset binary data outputs (D13 to D0; D13 is the MSB and D0 is the
LSB), a data-ready signal (DRY), and an over-range indicator (OVR). It is recommended to use the DRY signal
to capture the output data of the ADS5474. DRY is source-synchronous to the DATA/OVR outputs and operates
at the same frequency, creating a half-rate DDR interface that updates data on both the rising and falling edges
of DRY. It is recommended that the capacitive loading on the digital outputs be minimized. Higher capacitance
shortens the data-valid timing window. The values given for timing (see Figure 2) were obtained with a measured
10-pF parasitic board capacitance to ground on each LVDS line (or 5-pF differential parasitic capacitance). When
setting the time relationship between DRY and DATA at the receiving device, it is generally recommended that
setup time be maximized, but this partially depends on the setup and hold times of the device receiving the
digital data (like an FPGA or Field Programmable Field Array). Since DRY and DATA are coincident, it will likely
be necessary to delay either DRY or DATA such that setup time is maximized.
Referencing Figure 2, the polarity of DRY with respect to the sample N data output transition is undetermined
because of the unknown startup logic level of the clock divider that generates the DRY signal (DRY is a
frequency divide-by-two of CLK). Either the rising or the falling edge of DRY will be coincident with sample N and
the polarity of DRY could invert when power is cycled off/on or when the power-down pin is cycled. Data capture
from the transition and not the polarity of DRY is recommended, but not required. If the synchronization of
multiple ADS5474 devices is required, it might be necessary to use a form of the CLKIN signal rather than DRY
to capture the data.
The DRY frequency is identical on the ADS5474 and ADS5463 (where DRY equals ½ the CLK frequency), but
different than it is on the pin-similar ADS5444 (where DRY equals the CLK frequency). The LVDS outputs all
require an external 100-Ω load between each output pair in order to meet the expected LVDS voltage levels. For
long trace lengths, it may be necessary to place a 100-Ω load on each digital output as close to the ADS5474 as
possible and another 100-Ω differential load at the end of the LVDS transmission line to provide matched
impedance and avoid signal reflections. The effective load in this case reduces the LVDS voltage levels by half.
The OVR output equals a logic high when the 14-bit output word attempts to exceed either all 0s or all 1s. This
flag is provided as an indicator that the analog input signal exceeded the full-scale input limit of approximately
2.2 V_PP (± gain error). The OVR indicator is provided for systems that use gain control to keep the analog input
signal within acceptable limits.
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