CC1110FX_10 Datasheet, PDF (239/247 Pages) Texas Instruments – Low-Power SoC (System-on-Chip) with MCU, Memory, Sub-1 GHz RF Transceiver, and USB Controller

CC1110Fx / CC1111Fx
20 General Information
20.1 Document History
Revision
SWRS033
SWRS033A
SWRS033B
Date
2006.01.04
2006.05.11
2007.09.14
SWRS033C 2007.09.20
SWRS033D 2007.10.19
SWRS033E 2007.10.26
Description/Changes
First release
Preliminary status updated
First data sheet for released product.
Preliminary data sheets exist for engineering samples and pre-production prototype devices,
but these data sheets are not complete and may be incorrect in some aspects compared with
the released product.
Data sheet update before release of product.
- Operating frequency range changed to 391 - 464 MHz and 782 - 928 MHz
- Changed restricted range for PA power in Section 13.15 (now 0x68 to 0x6F)
- Added information about register TEST1 when TX-if-CCA is to be used
- Changed register FREQEST and FSCTRL0 max range from ±20910 to ±209
- Added reference to SmartRF Studio for register MCSM0.
- Changed bit description for bit FSCAL2.VCO_CORE_H_EN
- Added Section 12.1.5.2, describing data rate limitations caused by system clock speed
- Added power numbers for RX (Table 6) when using other system clock speeds
Data sheet update before release of CC1111Fx.
- Electrical Specification Section 6 updated with CC1111Fx performance
- Minimum power down time of CC1110Fx high speed crystal oscillator stated in Section 6.4.1,
Section 6.4.2, Section 12.1.1 and Section 12.1.5.1.
- Removed 3^rd overtone crystal option for CC1111Fx
- Replaced Figure 14, Figure 15, and Figure 16 to correct error in address ranges.
- Fixed Table 32
- Fixed bit range for register FADDRH and stated that register WORTIME0 and WORTIME1
defines a combined 16 bit word (WORTIME)
- Replaced all occurrences of WORCTL with WORCTRL
- Made consistent use of VDD for power with reference to power pin if so needed
- Corrected part number for these devices, register PARTNUM
- Stated that P1_0 and P1_1 does not have pull capability in register P2INP
- Corrected code example in Figure 49
- Corrected unimplemented RAM range in Section 10.2.3.1
- Updated Sections 12.1.3, 12.1.5.1, and 12.1.5.3 with information about system clock source
change
- Rewrote RAM range in Section 12.3.2
- Updated Section 12.8.2 with information about power modes. Changed code examples
- Changed heading text for Section 12.8.5
- Corrected received symbol write and read location in Section 13.11.2
- Corrected Table of contents
- Updated guard time and stated for which crystal this applies in Table 11
SWRS033G
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