TSC2102 Datasheet, PDF (23/54 Pages) Texas Instruments – PROGRAMMABLE TOUCH SCREEN CONTROLLER WITH INTEGRATED STEREO AUDIO DAC AND HEADPHONE AMPLIFIER

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TSC2102
SLAS379A− APRIL 2003 − REVISED JUNE 2004
D LEFT-JUSTIFIED MODE
In left−justified mode, the MSB of the right channel is valid on the rising edge of the BCLK following the falling edge of
LRCK. Similarly the MSB of the left channel is valid on the rising edge of the BCLK following the rising edge of LRCK.
1/fs
LRCK
BCLK
Left Channel
Right Channel
DIN
n n−1 n−2
210
n n−1 n−2
210
n n−1
MSB
LSB
Figure 19. Timing Diagram for Left-Justified Mode
D I2S MODE
In I2S mode, the MSB of the left channel is valid on the second rising edge of the BCLK after the falling edge of LRCK.
Similarly, the MSB of the right channel is valid on the second rising edge of the BCLK after the rising edge of LRCK.
1/fs
LRCK
BCLK
1 clock before MSB
Left Channel
Right Channel
DIN
n n−1 n−2
210
n n−1 n−2
210
n
MSB
LSB
Figure 20. Timing Diagram for I2S Mode
D DSP MODE
In DSP mode, the falling edge of LRCK starts the data transfer with the left channel data first and immediately followed
by the right channel data. Each data bit is valid on the falling edge of BCLK.
1/fs
LRCK
BCLK
Left Channel
Right Channel
DIN 1 0 n n−1 n−2
2 1 0 n n−1 n−2
2 1 0 n n−1 n−2
LSB MSB
LSB MSB
LSB MSB
Figure 21. Timing Diagram for DSP Mode
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