TPS7A8300 Datasheet, PDF (23/33 Pages) Texas Instruments – 2-A, 6-VRMS, RF, LDO Voltage Regulator

TPS7A8300
www.ti.com
SBVS197C – MAY 2013 – REVISED JULY 2013
Unfortunately, this thermal resistance (θ_JA) is highly dependent on the heat-spreading capability built into the
particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the
planes. The θ_JA recorded in the Thermal Information table is determined by the JEDEC standard, PCB, and
copper-spreading area and is to be used only as a relative measure of package thermal performance. Note that
for a well-designed thermal layout, θ_JA is actually the sum of the QFN package junction-to-case (bottom) thermal
resistance (θ_JCbot) plus the thermal resistance contribution by the PCB copper. When θ_JCbot is known, one can
estimate the amount of heat-sinking area required for a given θ_JA, refer to Figure 53. θ_JCbot can be found in the
Thermal Information table.
120
100
80
60
40
q_JA (RGW)
20
0
0 12 3 4 5 6 7 8
2
Board Copper Area (in )
NOTE: θ_JA value at a board size of 9-in² (that is, 3-in × 3-in) is a JEDEC standard.
Figure 53. θ_JA vs Board Size
9 10
Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the LDO while in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal
resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics
are determined to be significantly independent of copper-spreading area. The key thermal metrics (Ψ_JT and Ψ_JB)
are given in the Thermal Information table and are used in accordance with Equation 11.
Y_JT:
T
J
=
T
T
+
Y_JT
´
P
D
Y_JB: T_J = T_B + Y_JB ´ P_D
where:
• P_D is the power dissipated as explained in Equation 9,
• T_T is the temperature at the center-top of the device package, and
• T_B is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge.
(11)
BOARD LAYOUT
For best overall performance, place all circuit components on the same side of the circuit board and as near as
practical to the respective LDO pin connections. Place ground return connections to the input and output
capacitor, and to the LDO ground pin as close to each other as possible, connected by a wide, component-side,
copper surface. The use of vias and long traces to create LDO circuit connections is strongly discouraged and
negatively affects system performance. This grounding and layout scheme minimizes inductive parasitics, and
thereby reduces load-current transients, minimizes noise, and increases circuit stability.
A ground reference plane is also recommended and should be either embedded in the PCB itself or located on
the bottom side of the PCB opposite the components. This reference plane serves to assure accuracy of the
output voltage, shield noise, and behaves similar to a thermal plane to spread (or sink) heat from the LDO device
when connected to the PowerPAD™. In most applications, this ground plane is necessary to meet thermal
requirements.
Copyright © 2013, Texas Instruments Incorporated
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