TPS51200_1 Datasheet, PDF (23/35 Pages) Texas Instruments – SINK/SOURCE DDR TERMINATION REGULATOR

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Design Example 2
This design example describes a 3.3-V_IN, DDR3 Configuration
TPS51200
SLUS812 – FEBRUARY 2008
V_VDDQ = 1.5 V
V_VLDOIN = V_VDDQ = 1.5 V
V_VTT = 0.75 V
R1
10 kW
R2
10 kW
C4
1000 pF
TPS51200
1 REFIN
VIN 10
C7
10 mF
2 VLDOIN PGOOD 9
C8
10 mF
3.3 V_IN
R3
100 kW
C6
4.7 mF
PGOOD
3 VO
GND 8
C1 C2 C3
10 mF 10 mF 10 mF
4 PGND
EN 7
5 VOSNS REFOUT 6
C5
0.1 mF
SLP_S3
VTTREF
UDG-08029
REFERENCE
DESIGNATOR
R1, R2
R3
C1, C2, C3
C4
C5
C6
C7, C8
Figure 26. 3.3-V_IN, DDR3 Configuration
Design Example 2 List of Materials
DESCRIPTION
Resistor
Capacitor
SPECIFICATION
10 kΩ
100 kΩ
10 µF, 6.3 V
1000 pF
0.1 µF
4.7 µF, 6.3 V
10 µF, 6.3 V
PART NUMBER
GRM21BR70J106KE76L
GRM21BR60J475KA11L
GRM21BR70J106KE76L
MANUFACTURER
Murata
Murata
Murata
Copyright © 2008, Texas Instruments Incorporated
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Product Folder Link(s): TPS51200