TPA3200D1_07 Datasheet, PDF (23/27 Pages) Texas Instruments – 20-W MONO DIGITAL INPUT AUDIO AMPLIFIER

TPA3200D1
www.ti.com
SLOS442A – MAY 2005 – REVISED JULY 2005
SHUTDOWN OPERATION
The TPA3200D1 employs a shutdown mode of operation designed to reduce supply current (I_CC) to the absolute
minimum level during periods of non-use for battery-power conservation. The SHUTDOWN input terminal should
be held high during normal operation when the amplifier is in use. Pulling SHUTDOWN low causes the outputs to
mute and the amplifier to enter a low-current state, I_CC(SD) = 1 µA. SHUTDOWN should never be left
unconnected, because amplifier operation would be unpredictable.
Ideally, the device should be held in shutdown when the system powers up and brought out of shutdown once
any digital circuitry has settled. However, if SHUTDOWN is to be left unused, the terminal may be connected
directly to V_CC.
USING LOW-ESR CAPACITORS
Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitor
can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor
minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance
the more the real capacitor behaves like an ideal capacitor.
A metalized polyester capacitor is recommended for the capacitor placed in parallel across the FLT1 and FLT2
inputs. This ensures the best noise performance.
PRINTED-CIRCUIT BOARD (PCB) LAYOUT
Because the TPA3200D1 is a class-D amplifier that switches at a high frequency, the layout of the printed-circuit
board (PCB) should be optimized according to the following guidelines for the best possible performance.
• Decoupling capacitors — The high-frequency 1-µF decoupling capacitors should be placed as close to the
PVCC (pin 18 and pin 27) and VCC (pin 35) terminals as possible. The BYPASS (pin 33) capacitor, VREF
(pin 34) capacitor, and VCLAMP (pin 15) capacitor should also be placed as close to the device as possible.
The large (10 µF or greater) bulk power supply decoupling capacitor should be placed near the TPA3200D1
at the PVCC terminals.
• Grounding — The VCC (pin 35) decoupling capacitor, VREF (pin 34) capacitor, BYPASS (pin 33) capacitor,
COSC (pin 32) capacitor, and ROSC (pin 31) resistor should each be grounded to analog ground (AGND,
pin 29 and pin 30). The PVCC (pin 18 and pin 27) decoupling capacitors should each be grounded to power
ground (PGND pins 14, 21, 22, 23, and 24). Analog ground and power ground may be connected at the
PowerPAD, which should be used as a central ground connection, or star ground, for the TPA3200D1.
DGND (pins 5, 9, 38, and 40) should be connected to PGND, and AGND at the power supply through a
ferrite bead. Connect the VDD (pins 6 and 8) decoupling capacitor to DGND. This pattern separates the
digital power-switching currents and digital input currents, and prevents interference between them.
• Digital input signal routing — The SCLK, BCK, LRCK, and DATA input are sensitive, high-frequency signals
that should be shielded by a clean GND layer to avoid interference. For a 2-layer PCB, shield the signals on
the bottom layer with a plane connected to DGND. On the top layer, route DGND closely around these
signals.
• Output filter — The ferrite filter (Figure 24) should be placed as close to the output terminals (pins 19, 20, 25,
and 26) as possible for the best EMI performance. The LC filter (Figure 25 and Figure 26) should be placed
closest to the output and followed by a ferrite-bead filter. The capacitors used in both the ferrite and LC filters
should be grounded to power ground.
• PowerPAD — The PowerPAD must be soldered to the PCB for proper thermal performance and optimal
reliability. The dimensions of the PowerPAD thermal land on the PCB should be 3.5 mm by 9.5 mm. Three
rows of solid vias (six vias per row, 0.3302 mm or 13 mils diameter) should be equally spaced underneath
the thermal land. The vias should connect to a solid copper plane, either on an internal layer or on the
bottom layer of the PCB. The vias must be solid vias, not thermal relief or webbed vias. For additional
information, see the PowerPAD Thermally Enhanced Package technical brief, TI literature number SLMA002.
For an example layout, see the TPA3200D1 Evaluation Module (TPA3200D1EVM) User Manual, TI literature
number SLOU173. Both the EVM user manual and the PowerPAD application note are available on the TI web
site at http://www.ti.com.
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