TMS320VC5409 Datasheet, PDF (23/89 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR

Functional Overview
00 0000
Page 0
64K^†
0 FFFF
1 0000
1 7FFF
1 8000
Page 1
Lower
32K^‡
External
Page 1
Upper
32K
External
1 FFFF
2 0000
2 7FFF
2 8000
Page 2
Lower
32K^‡
External
Page 2
Upper
32K
External
2 FFFF
...
7F 0000
Page 127
Lower
32K^‡
External
...
7F 7FFF
...
7F 8000
Page 127
Upper
32K
External
...
7F FFFF
† _{Refer to Figure 1. 5409 Memory Map.}
‡ _{The Lower 32K words of pages 1 through 126 are available only when the OVLY bit is cleared to 0. If the OVLY bit is set to 1,}
the on-chip RAM is mapped to the lower 32K words of all program space pages.
Figure 3−6. Extended Program Memory
3.3 On-Chip Peripherals
The 5409 device has the following peripherals:
• An enhanced 8-bit host-port interface (HPI8/16) with 16-bit data/addressing
• Three multichannel buffered serial ports (McBSPs)
• One hardware timer
• A clock generator with a phase-locked loop (PLL)
• A direct memory access (DMA) controller
3.3.1 Parallel I/O Ports
The 5409 CPU has a total of 64K I/O ports. These ports can be addressed by the PORTR instruction or the
PORTW instruction. The IS signal indicates a read/write operation through an I/O port. The 5409 can interface
easily with external devices through the I/O ports while requiring minimal off-chip address-decoding circuits.
3.3.1.1 Enhanced 8-Bit Host-Port Interface (HPI8/16)
The 5409 host-port interface, also referred to as the HPI8/16, is an enhanced version of the standard 8-bit HPI
found on earlier 54x DSPs (542, 545, 548, and 549). The HPI8/16 is an 8-bit parallel port for interprocessor
communication. The features of the HPI8/16 include:
Standard features:
• Sequential transfers (with autoincrement) or random-access transfers
• Host interrupt and 54x interrupt capability
• Multiple data strobes and control pins for interface flexibility
Enhanced features of the 5409 HPI8/16:
• Access to entire on-chip RAM through DMA bus
• Capability to continue transferring during emulation stop
• Capability to transfer 16-bit address and 16-bit data (non-multiplexed mode)
April 1999 − Revised February 2004
SPRS082E
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