LM4308 Datasheet, PDF (23/33 Pages) Texas Instruments – LM4308 Mobile Pixel Link Two (MPL-2) 18-bit CPU Display Interface Master/Slave

LM4308
www.ti.com
SNLS225C – AUGUST 2007 – REVISED MAY 2013
• Use ground lines are guards to minimize any noise coupling (specifies distance).
• Avoid using multiple vias to reduce impedance mismatch and inductance.
• Use a GSSGSSG pinout in connectors (Board to Board or ZIF).
• Bypass the device with MLC surface mount devices and thinly separated power and ground planes with low
inductance feeds.
• High current returns should have a separate path with a width proportional to the amount of current carried to
minimize any resulting IR effects.
• Slave device - follow similar guidelines.
• see AN-1126 (SNOA021) (BGA) and AN-1187 (SNOA401) (WQFN) also
Connection Diagram csBGA Package
Ball A1
A
B
C
D
E
F
G
1
2
3
4
5
6
7
Figure 19. TOP VIEW
(not to scale)
Note that the pinout of a MASTER configured device is DIFFERENT than a SLAVE configured device. The use
of two logic symbols for PCB schematic is recommended.
MST
A
B
C
D
E
F
G
1
AD
CLK
WR*
V_DDIO
D0
D2
D4
2
CS1*
TM
CS2*
RD*
D1
D3
D5
Table 8. CPU Master Pinout
3
PD*
M/S*
V_SSIO
V_SSIO
V_SSIO
D6
D7
4
DCP_M
V_SSA
V_SSIO
V_SSIO
V_SSIO
V_SS
V_DD
5
DCN_M
V_DDA
V_SSIO
V_SSIO
V_SSIO
D9
D8
6
DDN_M
PLLCON0
ERR
D16
D14
D11
D10
7
DDP_M
PLLCON1
D17
V_DDIO
D15
D13
D12
SLV
A
B
C
D
E
1
AD
WO
WR*
V_DDIO
D0
2
CS1*
TM
CS2*
RD*
D1
Table 9. CPU Slave Pinout
3
PD*
M/S*
V_SSIO
V_SSIO
V_SSIO
4
DDP_S
V_SSA
V_SSIO
V_SSIO
V_SSIO
5
DDN_S
V_DDA
V_SSIO
V_SSIO
V_SSIO
6
DCN_S
RDS0
ERR
D16
D14
7
DCP_S
RDS1
D17
V_DDIO
D15
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