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CF4320H_09 Datasheet, PDF (23/29 Pages) Texas Instruments – CompactFlash™ BUS-INTERFACE CHIP WITH ±15-kV ESD PROTECTION, TRANSLATION, AND CARD-DETECT CIRCUITRY
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From Output
Under Test
CL
(see Note A)
CF4320H
CompactFlash™ BUS-INTERFACE CHIP
WITH ±15-kV ESD PROTECTION, TRANSLATION, AND CARD-DETECT CIRCUITRY
SCES655A – APRIL 2006 – REVISED AUGUST 2006
PARAMETER MEASUREMENT INFORMATION
VLOAD
RL
S1
Open
GND
RL
TEST
tpd
tPLZ/tPZL
tPHZ/tPZH
S1
Open
VLOAD
GND
LOAD CIRCUIT
VCC
1.8 V ± 0.15 V
2.5 ± 0.2 V
2.7 V
3.3 V ± 0.3 V
5.5 V ± 0.5 V
INPUT
VI
tr/tf
VCC
VCC
2.7 V
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
≤2.5 ns
VM
VCC/2
VCC/2
1.5 V
1.5 V
1.5 V
VLOAD
2 × VCC
2 × VCC
6V
6V
6V
CL
15 pF
15 pF
15 pF
15 pF
15 pF
RL
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
V∆
0.15 V
0.15 V
0.3 V
0.3 V
0.5 V
Timing
Input
Data
Input
VI
VM
0V
tsu
th
VI
VM
VM
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Input
VM
VI
VM
0V
tPLH
tPHL
Output
VOH
VM
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Input
tw
VM
VI
VM
0V
VOLTAGE WAVEFORMS
PULSE DURATION
Output
Control
(low-level
VM
enabling)
VI
VM
0V
tPZL
Output
Waveform 1
S1 at VLOAD
VM
(see Note B)
tPLZ
VOL + V∆
VLOAD/2
VOL
tPZH
Output
Waveform 2
S1 at GND
VM
(see Note B)
tPHZ
VOH − V∆
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
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