AFE8221 Datasheet, PDF (23/48 Pages) Texas Instruments – Dual IF Analog Front-End for Digital Radio

AFE8221
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DIGITAL DOWNCONVERTER 1 (DDC1)
The description of DDC1 is identical to the description
of DDC0, with the following exceptions:
1. DDC1 is enabled by ddc_en[1].
2. Control variables are prefixed with ddc1 instead
of ddc0.
3. FIR coefficients are stored in memory banks 3, 4,
and 5 instead of 0, 1, and 2.
Table 5 shows the DDC1 operation control settings.
PRIMARY IF DATA INTERFACE
The two DDCs produce a total of eight 16-bit output
values (I and Q from each of four final-stage FIR
filters). The IF data interface time-multiplexes these
eight values onto four serial lines. The IF data
interface also generates the necessary clock and
frame sync signals to complete the interface to the
DSP. The general timing of the IF data interface is
shown in Figure 15.
Note that each serial line (IF_DOUT0 through
IF_DOUT3) can carry up to four time-multiplexed
16-bit signals. The actual number of signals per line
is limited by:
a. the frequency of IF_DCLK, which can be
programmed to be the same as the IF sampling
clock (MCLK), one-half the IF sampling
frequency, or one-fourth the IF sampling
frequency; and
b. the overall decimation ratio of the DDC that
determines the frequency of IF_DFSO pulses and
therefore the number of IF_DCLK cycles
available to clock out data.
SBAS394A – APRIL 2007 – REVISED MARCH 2008
Table 5. IF Control Register Settings
PARAMETER
ddc1_cic_dec_rate
ddc1_cic_scale
ddc1_cic_shift
ddc1_demod_freq[31:16]
ddc1_demod_freq[15:0]
ddc1_demod_phase[31:16]
ddc1_demod_phase[15:0]
ddc1_fir1_base_address
ddc1_fir1_mode
ddc1_fir1_ncoeffs
ddc1_fir1_nodec
ddc1_fir2_nodec
ddc1_fir2a_base_address
ddc1_fir2a_mode
ddc1_fir2a_ncoeffs
ddc1_fir2a_shift
ddc1_fir2b_base_address
ddc1_fir2b_mode
ddc1_fir2b_ncoeffs
ddc1_fir2b_shift
ddc1_interleave
ddc_en[1]
ddc_sync
ADDRESS
21
22
22
17
18
19
20
23
23
23
26
26
24
24
24
26
25
25
25
26
26
1
1
BITS
8:0
11:6
5:0
15:0
15:0
15:0
15:0
13:8
1:0
7:2
9
10
15:9
1:0
8:2
3:0
15:9
1:0
8:2
7:4
8
5
6
IF_DCLK
IF_DFSO
IF_DOUT0
IF_DOUT1
IF_DOUT2
IF_DOUT3
A0[15:0]
A1[15:0]
A2[15:0]
A3[15:0]
B0[15:0]
B1[15:0]
B2[15:0]
B3[15:0]
C0[15:0]
C1[15:0]
C2[15:0]
C3[15:0]
Figure 15. IF Data General Timing
D0[15:0]
D1[15:0]
D2[15:0]
D3[15:0]
Copyright © 2007–2008, Texas Instruments Incorporated
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