ADS8556 Datasheet, PDF (23/40 Pages) Texas Instruments – 16-14-12-Bit Six-Channel Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTERS

ADS8556
ADS8557
ADS8558
www.ti.com ............................................................................................................................................... SBAS404A – OCTOBER 2006 – REVISED AUGUST 2009
GENERAL DESCRIPTION
The ADS8556/7/8 series include six 16-, 14-, and
12-bit analog-to-digital converters (ADCs)
respectively that operate based on the successive
approximation register (SAR) principle. The
architecture is designed on the charge redistribution
principle, which inherently includes a
sample-and-hold function. The six analog inputs are
grouped into three channel pairs. These channel
pairs can be sampled and converted simultaneously,
preserving the relative phase information of the
signals of each pair. Separate conversion start
signals allow simultaneous sampling on each channel
pair: on four channels or on all six channels.
These devices accept single-ended, bipolar analog
input signals in the selectable ranges of ±4V_REF or
±2V_REF with an absolute value of up to ±12V; see the
Analog Inputs section.
The devices offer an internal 2.5V/3V reference
source followed by a 10-bit digital-to-analog converter
(DAC) that allows the reference voltage V_REF to be
adjusted in 2.44mV or 2.93mV steps, respectively.
The ADS8556/7/8 also offer a selectable parallel or
serial interface that can be used in hardware or
software mode; see the Device Configuration section
for details.
period, there is no further input current flow and the
input impedance is greater than 1MΩ. To ensure a
defined start condition, the sampling capacitors of the
ADS8556/7/8 are pre-charged to a fixed internal
voltage, before switching into sampling mode.
To maintain the linearity of the converter, the inputs
should always remain within the specified range of
HVSS – 0.2V to HVDD + 0.2V.
The minimum –3dB
operational amplifier
Equation 1:
ln(2) ´ (n + 1)
f_-3dB =
2p ´ t_ACQ
bandwidth of the driving
can be calculated using
(1)
where:
n = 16, 14, or 12; n is the resolution of the
ADS8556/7/8
With a minimum acquisition time of t_ACQ = 280ns, the
required minimum bandwidth of the driving amplifier
is 6.7MHz for the ADS8556, 6MHz for the ADS8557,
or 5.2MHz for the ADS8558. The required bandwidth
can be lower if the application allows a longer
acquisition time. A gain error occurs if a given
application does not fulfill the bandwidth requirement
shown in Equation 1.
ANALOG
This section addresses the analog input circuit, the
ADCs and control signals, and the reference design
of the device.
Analog Inputs
The inputs and the converters are of single-ended,
bipolar type. The absolute voltage range can be
selected using the RANGE pin (in hardware mode) or
RANGE_x bits (in software mode) in the control
register (CR) to either ±4V_REF or ±2V_REF. With the
reference set to 2.5V (CR bit C18 = 0), the input
voltage range can be ±10V or ±5V. With the
reference source set to 3V (CR bit C18 = 1), an input
voltage range of ±12V or ±6V can be configured. The
logic state of the RANGE pin is latched with the
falling edge of BUSY (if CR bit C20 = 0).
The input current on the analog inputs depends on
the actual sample rate, input voltage, and signal
source impedance. Essentially, the current into the
analog inputs charges the internal capacitor array
only during the sampling period (t_ACQ). The source of
the analog input voltage must be able to charge the
input capacitance of 10pF in ±4V_REF mode or 20pF in
±2V_REF to a 12-, 14-, 16-bit accuracy level within the
acquisition time of 280ns at maximum data rate; see
the Equivalent Input Circuit. During the conversion
A driving operational amplifier may not be required, if
the impedance of the signal source (R_SOURCE) fulfills
the requirement of Equation 2:
R_SOURCE <
t_ACQ
C_S ln(2) ´ (n + 1)
- (R_SER + R_SW)
(2)
where:
n = 16, 14, or 12; n is the resolution of the ADC,
C_S = 10pF is the sample capacitor value for V_IN =
±4 × V_REF mode,
R_SER = 200Ω is the input resistor value,
and R_SW = 130Ω is the switch resistance value
With t_ACQ = 280ns, the maximum source impedance
should be less than 2.0kΩ for the ADS8556, 2.3kΩ
for the ADS8557, and 2.7kΩ for the ADS8558 in V_IN
= ±4V_REF mode or less than 0.8kΩ for the ADS8556,
1.0kΩ for the ADS8557, and 1.2kΩ for the ADS8558
in V_IN = ±2V_REF mode. The source impedance can be
higher if the application allows longer acquisition time.
Analog-to-Digital Converter (ADC)
The devices include six ADCs that operate with either
an internal or an external conversion clock. The
conversion time can be as low as 1.09µs with internal
conversion clock (ADS8558). When an external clock
and reference are used, the minimum conversion
time is 925ns.
Copyright © 2006–2009, Texas Instruments Incorporated
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