ADS54T02_15 Datasheet, PDF (23/49 Pages) Texas Instruments – Dual Channel 12-Bit 750 Msps Receiver and Feedback IC

ADS54T02
www.ti.com
SLAS933B – JANUARY 2013 – REVISED JANUARY 2014
INTERLEAVING CORRECTION
Each of the two data converter channels consists of two interleaved ADCs each operating at half of the ADC
sampling rate but 180º out of phase from each other. The front end track and hold circuitry is operating at the full
ADC sampling rate which minimizes the timing mismatch between the two interleaved ADCs. In addition the
ADS54T02 is equipped with internal interleaving correction logic that can be enabled via SPI register write.
Input
Track &
Hold
Fs
ADC
ODD
Fs/2
0 deg
ADC
EVEN
Interleaving
Correction
Estimator
Fs/2
180 deg
The interleaving operation creates 2 distinct and interleaving products:
• Fs/2 – Fin: this spur is created by gain timing mismatch between the ADCs. Since internally the front end
track and hold is operated at the full sampling rate, this component is greatly improved and mostly dependent
on gain mismatch.
• Fs/2 Spur: due to offset mismatch between ADCs
Input
Signal
Fs/2 - Fin
Fs/2 Spur
Fs/2
The auto correction loop can be enabled via SPI register write in address 0x01. By default it is disabled for
lowest possible power consumption. The default settings for the auto correction function should work for most
applications. However please contact Texas Instruments if further fine tuning of the algorithm is required.
The auto correction function yields best performance for input frequencies below 250MHz.
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