ADS5484 Datasheet, PDF (23/37 Pages) Texas Instruments – 16-Bit, 170/200-MSPS Analog-to-Digital Converters

ADS5484
ADS5485
www.ti.com ............................................................................................................................................... SLAS610C – AUGUST 2008 – REVISED OCTOBER 2009
SFDR
vs
CLOCK AMPLITUDE
110
f_IN = 100.33 MHz f_IN = 30.13 MHz ^fIN ^{= 9.97 MHz}
100
90
80
70
f_IN = 69.59 MHz
f_IN = 170.13 MHz
60
f_IN = 130.13 MHz
f_S = 170 MSPS
50
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Clock Amplitude − V_PP
G035
Figure 39.
SNR
vs
CLOCK AMPLITUDE
81
79
f_IN = 69.59 MHz
f_IN = 30.13 MHz
f_IN = 9.97 MHz
77
75
73
f_IN = 130.13 MHz
71
69
f_IN = 100.33 MHz
67
65
0.0
f_IN = 170.13 MHz
f_S = 170 MSPS
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Clock Amplitude − V_PP
G036
Figure 40.
For jitter-sensitive applications, the use of a differential clock has some advantages at the system level. The
differential clock allows for common-mode noise rejection at the printed circuit board (PCB) level. With a
differential clock, the signal-to-noise ratio of the ADC is better for jitter-sensitive, high-frequency applications
because the board level clock jitter is superior.
The sampling process is more sensitive to jitter using high analog input frequencies or slow clock frequencies.
Large clock amplitude levels are recommended when possible to reduce the indecision (jitter) in the ADC clock
input buffer. Whenever possible, the ideal combination is a differential clock with large signal swing (~1 – 3 V_PP).
Figure 41 demonstrates a recommended method for converting a single-ended clock source into a differential
clock; it is similar to the configuration found on the evaluation board and was used for much of the
characterization. See also Clocking High Speed Data Converters (SLYT075) for more details.
Clock
Source
0.1 mF
CLKP
ADS548x
CLKM
S0194-03
Figure 41. Differential Clock
The common-mode voltage of the clock inputs is set internally to ~2 V using internal 0.5-kΩ resistors. It is
recommended to use ac coupling, but if this scheme is not possible, the ADS548x features good tolerance to
clock common-mode variation (as shown in Figure 42 and Figure 43). The internal ADC core uses both edges of
the clock for the conversion process. Ideally, a 50% duty-cycle clock signal should be provided. Performance
degradation as a result of duty cycle can be seen in Figure 44.
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