UCD9248 Datasheet, PDF (22/32 Pages) Texas Instruments – Digital PWM System Controller

UCD9248
SLVSA33 – JANUARY 2010
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Output Current Balancing
When the UCD9248 is configured to drive multiple power stage circuits from one compensator, current balancing
is implemented by adjusting each gate drive output pulse width to correct for current imbalance between the
connected power stage sections. The UCD9248 balances the current by monitoring the current at the CS analog
input for each power stage and then adding a current balance adjustment value to the DPWM ramp threshold
value for each power stage.
When there is more than one power stage connected to the voltage rail, the device continually determines which
stage has the highest measured current and which stage has the lowest measured current. To balance the
currents while maintaining a constant total current, the adjustment value for the power stage with the lowest
current is increased by the same amount as the adjustment value for the power stage with the highest current is
decreased. A slight modification to this algorithm is made to keep the adjustment values positive in order to
ensure that a positive DPWM duty cycle is commanded under all conditions.
Over-Current Detection
Several mechanisms are provided to sense output current fault conditions. This allows for the design of power
systems with multiple layers of protection.
1. An integrated gate driver, such as the UCD72xx of integrated gate drivers, can be used to generate the
FAULT signal. The driver monitors the voltage drop across the high side FET and if it exceeds a
resistor/voltage programmed threshold, the driver activates its fault output. The FAULT input can be disabled
by reconfiguring the FAULT pin to be a sequencing pin. A logic high signal on the FAULT input causes a
hardware interrupt to the internal CPU. The CPU then determines which DPWM outputs are configured to be
associated with the voltage rail that contained the fault and disables those DPWM and SRE outputs. This
process takes about 14 microseconds.
2. Inputs CS-1A, CS-2A, CS-3A and CS-4A each drive an internal analog comparator. These comparators can
be used to detect the voltage output of a current sense circuit. Each comparator has a separate PMBus
configurable threshold. This threshold is set by issuing the FAST_OC_FAULT_LIMIT command. Though the
command is specified in amperes, the hardware threshold is programmed with a value between 31mV and
2V in 64 steps. The conversion from amperes to volts is accomplished by issuing the IOUT_CAL_GAIN
command. When the current sense voltage exceeds the configured threshold the corresponding DPWM and
SRE outputs are driven low on the voltage rail with the fault.
3. Each Current Sense input to the UCD9248 is also monitored by the 12-bit ADC. Each measured value is
scaled using the IOUT_CAL_GAIN and IOUT_CAL_OFFSET commands. The currents for each power stage
configured as part of a voltage rail are summed and compared to the OC limit set by the
IOUT_OC_FAULT_LIMIT command. The action taken when a fault is detected is defined by the
IOUT_OC_FAULT_RESPONSE command.
Because the current measurement is averaged with a smoothing filter, the response time to an over-current
condition depends on a combination of the time constant (t) from Table 4, the recent measurement history, and
how much the measured value exceeds the over-current limit. When the current steps from a current (I₁) that is
less than the limit to a higher current (I₂) that is greater than the limit, the output of the smoothing filter is:
( ) ^Ismoothed ^{(t) = I}1 ^{+ (I}2 ^{- I}1^{) 1 - e-t/t}
(11)
At the point when Ismoothed exceeds the limit, the smoothing filter lags time, t_lag is:
t_lag
=
t
ln
æ
ç
I₂
è ^I2
- I₁
- I_limit
ö
÷
ø
(12)
The worst case response time to an over-current condition is the sum of the sampling interval (see Table 4) and
the smoothing filter lag, t_lag from the equation above.
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