TVP5154 Datasheet, PDF (22/78 Pages) Texas Instruments – 4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER WITH INDEPENDENT SCALERS AND FAST LOCK

TVP5154
4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER
WITH INDEPENDENT SCALERS AND FAST LOCK
SLES163A – MARCH 2006 – REVISED JULY 2006
Table 9-1. Direct Register Summary (continued)
REGISTER FUNCTION
VDP configuration RAM data
Configuration RAM address low byte
Configuration RAM address high byte
VDP status register
FIFO word count
FIFO interrupt threshold
FIFO reset
Line number interrupt
Pixel alignment register low byte
Pixel alignment register high byte
FIFO output control
Reserved
Full field enable
Line mode registers
Full field mode register
Reserved
Decoder core write enables
Decoder core read enables
ADDRESS
C3h
C4h
C5h
C6h
C7h
C8h
C9h
CAh
CBh
CCh
CDh
CEh
CFh
D0h
D1h–FBh
FCh
FDh
FEh
FFh
DEFAULT
B8h
1Fh
00h
80h
00h
00h
4Eh
00h
01h
00h
00h
FFh
7Fh
0Fh
00h
9.2 Direct Register Definitions
Direct registers are written to by performing a 3-byte I²C transaction:
START : DEVICE_ID : SUB_ADDRESS : DATA : STOP
Each direct register is eight bits wide.
9.2.1 Video Input Source Selection #1 Register
Address
00h
Default
00h
7
6
5
4
Reserved
Channel n source selection:
0 = AIPnA selected (default)
1 = AIPnB selected
3
Black output
2
Reserved
1
Channel n source selection
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R/W ⁽¹⁾
R/W
R/W
R/W
R
R
R/W
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
S-video selection
22
Internal Control Registers
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