TPS2220B Datasheet, PDF (22/27 Pages) Texas Instruments – POWER-INTERFACE SWITCHES FOR SERIAL PCMCIA CONTROLLERS

TPS2220B
SLVS554 – JANUARY 2005
APPLICATION INFORMATION (continued)
TPS2220B CONTROL LOGIC
AVPP
AVPP CONTROL SIGNALS
D8 (SHDN)
D0
D1
D9
1
0
0
X
1
0
1
0
1
0
1
1
1
1
0
X
1
1
1
X
0
X
X
X
OUTPUT
V_AVPP
0V
3.3 V
5V
12 V
Hi-Z
Hi-Z
AVCC
AVCC CONTROL SIGNALS
D8 (SHDN)
D3
D2
1
0
0
1
0
1
1
1
0
1
1
1
0
X
X
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OUTPUT
V_AVCC
0V
3.3 V
5V
0V
Hi-Z
ESD PROTECTIONS (see Figure 35)
All inputs and outputs of these devices incorporate ESD-protection circuitry designed to withstand a 2-kV
human-body-model discharge as defined in MIL-STD-883C, Method 3015. The AVCC and AVPP outputs can be
exposed to potentially higher discharges from the external environment through the PC Card connector.
Bypassing the outputs with 0.1-µF capacitors protects the devices from discharges up to 10 kV.
12 V
5V
4.7 µF
0.1 µF
4.7 µF
0.1 µF
3.3 V
4.7 µF
0.1 µF
TPS2220B
AVCC
AVCC
12 V
AVPP
5V
5V
3.3 V
DATA
CLOCK
LATCH
RESET
OC
0.1 µF^†
0.1 µF^†
V_CC
V_CC
PC Card
Connector A
V_pp1
V_pp2
From PCI or
System RST
Controller
DATA
CLOCK
LATCH
GPI/O
† _{Maximum recommended output capacitance for AVCC is 220 µF including card capacitance, and for AVPP is 10 µF, without OC glitch when}
switches are powered on.
Figure 35. Detailed Interconnections and Capacitor Recommendations
22