TMS320C54V90 Datasheet, PDF (22/87 Pages) Texas Instruments – EMBEDDED V.90 MODEM DSP

TMS320C54V90
EMBEDDED V.90 MODEM DSP
SPRS165F − JULY 2001 − REVISED OCTOBER 2003
HPI control register bits and function (continued)
15–4
X
LEGEND: X = Unknown value is read.
3
HINT
2
1
0
0 SMOD 0
Figure 7. HPIC Diagram - DSP Reads from HPIC
15–4
X
LEGEND: X = Any value can be written.
3
HINT
2
1
0
X SMOD X
Figure 8. HPIC Diagram - DSP Writes to HPIC
Because the DSP can write to the SMOD and HINT bits, and these bits are read twice on the host interface side,
the first and second byte reads by the host may yield different data if the DSP changes the state of one or both
of these bits in between the two read operations. The characteristics of host and DSP HPIC read/write cycles
are summarized in Table 8.
Table 8. DSP HPIC Read/Write Cycles
DEVICE
Host
DSP
READ
2 bytes
16 bits
WRITE
2 bytes (Both bytes must be equal)
16 bits
host read/write access to HPI
The host begins HPI accesses by performing the external interface portion of the cycle; that is, initializing first
the HPIC register, then the HPIA register, and then writing data to or reading data from the HPID register. Writing
to HPIA or HPID initiates an internal cycle that transfers the desired data between the HPID and the dedicated
internal HPI memory. Because this process requires several DSP cycles, each time an HPI access is made,
data written to the HPID is not written to the HPI memory until after the host access cycle, and the data read
from the HPID is the data from the previous cycle. Therefore, when reading, the data obtained is the data from
the location specified in the previous access, and the current access serves as the initiation of the next cycle.
A similar sequence occurs for a write operation: the data written to HPID is not written to HPI memory until after
the external cycle is completed. If an HPID read operation immediately follows an HPID write operation, the
same data (the data written) is read.
The autoincrement feature available for HPIA results in sequential accesses to HPI memory by the host being
extremely efficient. During random (nonsequential) transfers or sequential accesses with a significant amount
of time between them, it is possible that the DSP may have changed the contents of the location being accessed
between a host read and the previous host data read/write or HPIA write access, because of the prefetch nature
of internal HPI operation. If this occurs, data different from the current memory contents may be read. Therefore,
in cases where this is of concern in a system, two reads from the same address or an address write prior to the
read access can be made to ensure that the most recent data is read.
When the host performs an external access to the HPI, there are two distinctly different types of cycles that can
occur: those for which wait states are generated (the HRDY signal is active) and those without wait states.
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