OPA2822 Datasheet, PDF (22/27 Pages) Texas Instruments – Dual, Wideband, Low-Noise Operational Amplifier

output signal and load but would, for a grounded resistive load,
be at a maximum when the output is fixed at a voltage equal
to half of either supply voltage (assuming equal bipolar sup-
plies). Under this condition P_DL = V_S2/(4 • R_L) where R_L
includes feedback network loading.
Note that it is the power dissipated in the output stage and not in
the load that determines internal power dissipation. As a worst-
case example, compute the maximum T_J for the OPA2822E with
both channels operating at A_V = +2, R_L = 100Ω, R_F = 400Ω,
±V_S = ±5V, and at the specified maximum T_A = 85°C.
P_D = 10V • 11.4mA + 2 • (5²)/(4 • (100 || 804)) = 255mW
Maximum T_J = 85°C + 0.255W • 150°C/W = 123°C
This calculation represents a worst-case combination of
conditions to reach a maximum possible operating junction
temperature. Under most operating conditions, the junction
temperature will be far lower than the 123°C calculated here.
The output current is limited in the OPA2822 to protect
against damage under short-circuit conditions. This current-
limited output of approximately 220mA exceeds the rated
typical output current of 150mA. The typical and minimum
output current limits are set for linear operation while the
maximum output shown in the Typical Characteristics is
nonlinear limited performance.
BOARD LAYOUT
Achieving optimum performance with a high-frequency am-
plifier like the OPA2822 requires careful attention to board
layout parasitics and external component types. Recommen-
dations that will optimize performance include:
a) Minimize parasitic capacitance to any AC ground for all
of the signal I/O pins. Parasitic capacitance on the output and
inverting input pins can cause instability: on the noninverting
input, it can react with the source impedance to cause
unintentional bandlimiting. To reduce unwanted capacitance,
a window around the signal I/O pins should be opened in all
of the ground and power planes around those pins. Other-
wise, ground and power planes should be unbroken else-
where on the board.
b) Minimize the distance (< 0.25") from the power-supply
pins to high-frequency 0.1µF decoupling capacitors. At the
device pins, the ground and power plane layout should not
be in close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance between
the device pins and the decoupling capacitors. The primary
power-supply connections (on pins 4 and 8) should always
be decoupled with these capacitors. Larger (2.2µF to 6.8µF)
decoupling capacitors, effective at lower frequencies, should
also be used on the main supply pins. These may be placed
somewhat farther from the device and may be shared among
several devices in the same area of the PC board.
c) Careful selection and placement of external compo-
nents will preserve the high-frequency performance of
the OPA2822. Resistors should be a very low reactance
type. Surface-mount resistors work best and allow a tighter
overall layout. Metal film and carbon composition axially
leaded resistors can also provide good high-frequency per-
formance. Again, keep their leads and PC board trace length
as short as possible. Never use wire-wound type resistors in
a high-frequency application. Since the output pin and invert-
ing input pin are the most sensitive to parasitic capacitance,
always position the feedback and series output resistor, if
any, as close as possible to the output pin. Other network
components, such as noninverting input termination resis-
tors, should also be placed close to the package. Even with
a low parasitic capacitance shunting the external resistors,
excessively high resistor values can create significant time
constants that can degrade performance. Good axial metal
film or surface-mount resistors have approximately 0.2pF in
shunt with the resistor. For resistor values > 1.5kΩ, this
parasitic capacitance can add a pole and/or zero below
500MHz that can effect circuit operation. Keep resistor val-
ues as low as possible consistent with parasitic load, distor-
tion, and noise considerations. The 402Ω feedback used in
the Typical Characteristics is a good starting point for design.
d) Connections to other wideband devices on the board may
be made with short direct traces or through onboard transmission
lines. For short connections, consider the trace and the input to
the next device as a lumped capacitive load. Relatively wide
traces (50mils to 100mils) should be used, preferably with ground
and power planes opened up around them. Estimate the total
capacitive load and set R_S from the plot of recommended R_S
versus capacitive load. If a long trace is required, and the 6dB
signal loss intrinsic to a doubly-terminated transmission line is
acceptable, implement a matched impedance transmission line
using microstrip or stripline techniques (consult an ECL design
handbook for microstrip and stripline layout techniques). A 50Ω
environment is normally not necessary onboard, and in fact a
higher impedance environment will improve distortion as shown
in the distortion versus load plots. With a characteristic board
trace impedance defined based on board material and trace
dimensions, a matching series resistor into the trace from the
output of the OPA2822 is used as well as a terminating shunt
resistor at the input of the destination device. Remember also that
the terminating impedance will be the parallel combination of the
shunt resistor and the input impedance of the destination device;
this total effective impedance should be set to match the trace
impedance. Multiple destination devices are best handled as
separate transmission lines, each with their own series and shunt
terminations. If the 6dB attenuation of a doubly-terminated trans-
mission line is unacceptable, a long trace can be series-termi-
nated at the source end only. Treat the trace as a capacitive load
in this case and set the series resistor value as shown in the plot
of R_S vs Capacitive Load. This will not preserve signal integrity as
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OPA2822
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