OPA180 Datasheet, PDF (22/38 Pages) Texas Instruments – OPAx180 0.1-μV/°C Drift, Low-Noise, Rail-to-Rail Output, 36-V, Zero-Drift Operational Amplifiers

OPA180, OPA2180, OPA4180
SBOS584D – NOVEMBER 2011 – REVISED MAY 2014
11 Layout
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11.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground
planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically
separate digital and analog grounds paying attention to the flow of the ground current. For more detailed
information refer to the Circuit Board Layout Techniques (SLOA089).
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace
perpendicular as opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As shown in Figure 35, keeping RF
and RG close to the inverting input will minimize parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
11.2 Layout Example
RIN
VIN
+
RG
VOUT
RF
(Schematic Representation)
Run the input traces
as far away from
the supply lines
as possible
Place components
close to device and to
each other to reduce
parasitic errors
RG
GND
RF
NC
±IN
VIN
+IN
RIN
V±
NC
V+
OUT
NC
VS+
GND
Use low-ESR, ceramic
bypass capacitor
Only needed for
dual-supply
operation
GND
VS±
(or GND for single supply)
VOUT
Ground (GND) plane on another layer
Figure 35. Operational Amplifier Board Layout for Noninverting Configuration
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