LMX2571_15 Datasheet, PDF (22/61 Pages) Texas Instruments – LMX2571 Low-Power, High-Performance PLLatinum™ RF Synthesizer with FSKModulation

LMX2571
SNAS654 – MARCH 2015
Bit Field
0
LD_EN
Table 8. R39 Register Field Descriptions (continued)
Type
R/W
Reset
0h
Description
Enables lock detect function.
0 = Disabled
1 = Enabled
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7.6.9 R35 Register (offset = 23h) [reset = 647h]
Figure 28. R35 Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
MULT_WAIT
OUTB
UF_A
UTOM
UTE
OUTB
UF_TX
_TYPE
OUTB
UF_R
X_TYP
E
R/W-0h
R/W-C8h
R/W- R/W- R/W-
1h
1h
1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit
15-14
13-3
Field
MULT_WAIT
2
OUTBUF_AUTOMUTE
1
OUTBUF_TX_TYPE
0
OUTBUF_RX_TYPE
Table 9. R35 Register Field Descriptions
Type
R/W
R/W
Reset
0h
C8h
R/W
1h
R/W
1h
R/W
1h
Description
Program 0h to this field.
A 20-µs settling time is required for MULT, if it is enabled. These
bits set the correct settling time according to the OSCin
frequency. For example, if OSCin frequency is 100 MHz, set
these bits to 2000. No matter if MULT is enabled or not, the
configured MULT settling time forms part of the total frequency
switching time.
0 = Do not use this setting
1 = 1 OSCin clock cycle
...
2047 = 2047 OSCin clock cycles
If this bit is set, the output buffers will be muted until PLL is
locked. This bit applies to the following events: (a) device
initialization (b) manually change VCO frequency, and (c) F1F2
switching. However, if the PLL is unlocked afterward (for
example, OSCin is removed), the output buffers will not be
muted and will remain active.
0 = Disabled
1 = Enabled
Sets the output buffer type of RFoutTx. If the buffer is open drain
output, a pullup to VccIO is required. See RF Output Buffer Type
for details.
0 = Open drain
1 = Push pull
Sets the output buffer type of RFoutRx. If the buffer is open
drain output, a pullup to VccIO is required. See RF Output Buffer
Type for details.
0 = Open drain
1 = Push pull
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