LM3639A Datasheet, PDF (22/28 Pages) Texas Instruments – Single Chip 40V Backlight + 1.5A Flash LED Driver

LM3639A
SNVS964 – MARCH 2013
www.ti.com
The following lists the main (layout sensitive) areas of the LM3639A in order of decreasing importance:
Output Capacitor
• Schottky Cathode to COUTB+
• COUTB− to GND
Schottky Diode
• SWB Pin to Schottky Anode
• Schottky Cathode to COUTB+
Inductor
• SWB Node PCB capacitance to other traces
Input Capacitor
• CIN+ to VIN pin
• CIN− to GND
Backlight Output Capacitor Placement
The output capacitor is in the path of the inductor current discharge current. As a result, C_OUTB sees a high
current step from 0 to I_PEAK each time the switch turns off and the Schottky diode turns on. Typical turn-off/turn-
on times are around 5 ns. Any inductance along this series path from the cathode of the diode through C_OUTB
and back into the LM3639A's GND pin will contribute to voltage spikes (V_SPIKE = L_PX × dI/dt) at SWB and OUTB
which can potentially over-voltage the SWB pin, or feed through to GND. To avoid this, C_OUTB+ must be
connected as close as possible to the cathode of the Schottky diode, and C_OUT− must be connected as close as
possible to the LM3639A's GND bump. The best placement for C_OUTB is on the same layer as the LM3639A to
avoid any vias that will add extra series inductance.
Schottky Diode Placement
The Schottky diode is in the path of the inductor current discharge. As a result the Schottky diode sees a high
current step from 0 to I_PEAK each time the switch turns off and the diode turns on. Any inductance in series with
the diode will cause a voltage spike (V_SPIKE = L_PX × dI/dt) at SW and OUT which can potentially over-voltage the
SW pin, or feed through to VOUT and through the output capacitor and into GND. Connecting the anode of the
diode as close as possible to the SW pin and the cathode of the diode as close as possible to COUT+ will
reduce the inductance (L_PX) and minimize these voltage spikes.
Backlight Inductor Placement
The node where the inductor connects to the LM3639A’s SW bump presents two challenges. First, a large
switched voltage (0 to V_OUT + V_{F_SCHOTTKY}) appears on this node every switching cycle. This switched voltage
can be capacitively coupled into nearby nodes. Second, there is a relatively large current (input current) on the
traces connecting the input supply to the inductor and connecting the inductor to the SW bump. Any resistance in
this path can cause large voltage drops that will negatively affect efficiency.
To reduce the capacitively coupled signal from SWB into nearby traces, the SW bump-to-inductor connection
must be minimized in area. This limits the PCB capacitance from SW to other traces. Additionally, other nodes
need to be routed away from SWB and not directly beneath. This is especially true for high-impedance nodes
that are more susceptible to capacitive coupling such as (SCL, SDA, EN, PWM). A GND plane placed directly
below SWB will help isolate SWB and dramatically reduce the capacitance from SW into nearby traces.
To limit the trace resistance of the VBATT-to-inductor connection and from the inductor-to-SW connection, use
short, wide traces.
Input Capacitor Selection and Placement
The input bypass capacitor filters the inductor current ripple, and the internal MOSFET driver currents, during
turn-on of the power switch.
The driver current requirement can be a few hundred mAs with 5 ns rise and fall times. This will appear as high
dI/dt current pulses coming from the input capacitor each time the switch turns on. Close placement of the input
capacitor to the IN pin and to the GND pin is critical since any series inductance between VIN and C_IN+ or C_IN−
and GND can create voltage spikes that could appear on the V_IN supply line and in the GND plane.
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