VSP1221 Datasheet, PDF (21/26 Pages) Texas Instruments – 12-BIT, 21-MSPS, ULTRALOW-POWER CCD SIGNAL PROCESSOR

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APPLICATION INFORMATION (continued)
Optical Black
Pixels
DIN
(CCD IN)
Dummy
Pixels
VSP1221
SLES012A – SEPTEMBER 2001 – REVISED JULY 2004
Active Image
Pixels
N N+1
SHP
SHD
CLPOB
BLKG
CLPDM
ADCCLK
D0–D11
N−9 N−8 N−7
12 Clocks
12 Clocks
OB Calibration Cycle
A. OB Calibration latency is 12 clocks. So, OB update starts 12 clocks after CLPOB is pulled low and stops 12 clocks
after CLPOB is pulled high.
B. If active image pixels are located immediately after CLPOB goes high, the OB update will affect the adjacent 12
pixels.
C. The device clocks are stopped during BLKG and CLPDM. Therefore, if these signals appear immediately after
CLPOB goes high, the OB calibration update for the subsequent 12 clocks will stop. So, its recommended to delay
BLKG and CLPDM by at least 12 pixels after CLPOB goes high.
Figure 10. System Timing Diagram Example
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