TSB42AA9 Datasheet, PDF (21/45 Pages) Texas Instruments – STORAGELYNX 1394 LINK-LAYER CONTROLLER FOR ATA/ATAPI STORAGE PRODUCTS

3.2.3 Control Register at 08h
Unless otherwise noted, all bits in this register are cleared to 0 at power up.
BIT NUMBER BIT NAME
DIR
DESCRIPTION
00
SFTRST
R Software controlled device reset. This bit is used by software to generate a reset.
01–02
Reserved
03
PAGEBIT
R/W Data memory page select. This bit is used by the embedded processor to select between two
banks of 256 bytes of data memory. The embedded processor is address limited to 256 bytes of
data memory. A 0 selects the lower 256 bytes of the 512 byte RAM used for processor data
memory space. A 1 selects the upper 256 bytes of the 512 byte RAM.
04
BSYCTL
R/W Busy control. This bit selects which busy state StorageLynx returns to an incoming packet. A 0
selects the normal busy/retry protocol, which only sends busy when necessary. A 1 selects a busy
acknowledge sent to all incoming packets.
05
TXEN
R/W Transmit enable. When this bit is cleared, the 1394 transmitter does not arbitrate or send packets.
This bit is set after a power-on reset.
06
RXEN
R/W Receive enable. When this bit cleared, the 1394 receiver does not receive any packets. This bit is
not affected by a bus reset and is set after a power-on reset.
07–09
Reserved
10
RSTTX
R/W Reset transmit. A 1 resets the entire transmitter synchronously. This bit clears itself.
11
RSTRX
R/W Reset receive. A 1 resets the entire receiver synchronously. This bit clears itself.
12, 13
Reserved
14
ENA_LHOLD R/W Enable long hold cycle. A 1 increases the hold time on a bus grant to 10 cycles.
15–22
Reserved
23
CLRSIDER
W Clear self-ID error. A 1 allows this bit to be automatic-cleared after one Nclock cycle.
24–26
Reserved
27
PWRON
R Power on switch signal. This bit drives the output signal PWRON. This signal is activated by
firmware in a power-on event.
28–31
Reserved
3.2.4 Interrupt and Interrupt Mask Register at 0C and 10h
The interrupt register is located at 0Ch and the interrupt mask register is located at 10h. The interrupt register powers
up with 0 in all bits. The interrupt mask register powers up with the INT mask bit set, i.e., 8000_0000h. The mask bits
allow individual control of each interrupt. A 1 in the mask bit field allows the corresponding interrupt in the Interrupt
register to be generated. Once an interrupt is generated it must be cleared by writing a 1 to the bit to be cleared in
the Interrupt register.
BIT NUMBER BIT NAME
DIR
DESCRIPTION
00
INT
R/W Interrupt. This bit contains the value of all interrupt and interrupt mask bits ORed together.
01
PHINT
R/W PHY interrupt. When this bit is set, the PHY has signaled an interrupt through the PHY interface.
02
PHRRX
R/W PHY register receive. When this bit is set, a register value has been transferred to the PHY Access
register (see section 3.2.9) from the PHY interface.
03
PHRST
R/W PHY reset. When this bit is set, a PHY-LLC reconfiguration has started (1394 bus reset).
04
SELFIDEND
R/W Self-ID end. This bit is set at the end of the self-ID reporting process and indicates the contents of
the bus reset CFR register (see section 3.2.13) are valid.
05
RXGRFPKT
R/W Receive packet to GRF. When this bit is set, a complete packet has been confirmed into the
general receive FIFO (GRF) interface.
06
CMDRST
R/W Command reset. When this bit is set, the receiver has been sent a quadlet write request
addressed to the RESET_START CSR register (see section 2.2.1).
07
SELFIDER
R/W Self-ID error. When this bit is set, an error in the self-ID process has been detected.
3–3