TRF7960_12 Datasheet, PDF(21/51 Page) Texas Instruments – MULTI-STANDARD FULLY INTEGRATED 13.56-MHZ RFID ANALOG FRONT END AND DATA-FRAMING READER SYSTEM

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TRF7960_12 Datasheet, PDF (21/51 Pages) Texas Instruments – MULTI-STANDARD FULLY INTEGRATED 13.56-MHZ RFID ANALOG FRONT END AND DATA-FRAMING READER SYSTEM

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TRF7960

TRF7961

www.ti.com

SLOU186F â AUGUST 2006 â REVISED AUGUST 2010

At the end of the transmit operation, the external system is notified by another interrupt request with a flag

in the IRQ register that signals the end of TX.

The TX length register also supports incomplete bytes transmitted. The high two nibbles in register 1D and

the nibble composed of bits B4âB7 in register 1E store the number of complete bytes to be transmitted.

Bit 0 (in register 1E) is a flag that signals the presence of additional bits to be transmitted that do not form

a complete byte. The number of bits are stored in bits B1âB3 of the same register (1E).

The protocol is selected by the ISO control register (address 01), which also selects the receiver protocol.

As defined by the selected protocol, the reader automatically adds all the special signals, like start of

communication, end of communication, SOF, EOF, parity bits, and CRC bytes. The data is then coded to

the modulation pulse level and sent to the modulation control of the RF output stage. This means that the

external system is only required to load the FIFO with data, and all the low-level coding is done

automatically. Also, all registers used in transmission are automatically preset to the optimum value when

a new selection is entered into the ISO control register.

Some protocols have options; two registers are provided to select the TX-protocol options. The first such

guard time) selection for the ISO14443B protocol. The bit definitions of this register are given in

Table 5-12.

The second register controls the ISO14443 high bit-rate options. This register enables the use of different

bit rates for RX and TX operations in the ISO14443 high bit-rate protocol. Additionally, it also selects the

parity system for the ISO14443A high bit-rate selection. The bit definitions of this register are given in

Table 5-13.

The transmit section also has a timer that can be used to start the transmit operation at a precise time

interval from a selected event. This is necessary if the tag requires a reply in an exact window of time

following the tag response. The TX timer uses two registers (addresses 04 and 05). In first register

(address 04); two bits (B7 and B6) are used to define the trigger conditions. The remaining 6 bits are the

upper bits and the 8 bits in register address 05 are lower bits, which are preset to the counter. The

increment is 590 ns and the range of this counter is from 590 ns to 9.7 ms. The bit definitions (trigger

conditions) are shown in Table 5-14.

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System Description

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