TPS65950A2ZXN Datasheet, PDF(21/171 Page) Texas Instruments – Integrated Power Management/Audio Codec

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TPS65950A2ZXN Datasheet, PDF (21/171 Pages) Texas Instruments – Integrated Power Management/Audio Codec

◁

TPS65950

www.ti.com

SWCS032E â OCTOBER 2008 â REVISED JANUARY 2011

Module

Signal

Name

SYSEN

CLKEN

CLKEN2

CLKREQ

INT1

INT2

NRESPWRON

NRESWARM

CONTROL

PWRON

NC

NSLEEP1

NSLEEP2

CLK256FS

VMODE1

BOOT0

BOOT1

REGEN

MSECURE

VREF

VREF

AGND

NC

I2C.SR.SDA

I2C

SmartReflex VMODE2

I2C

PCM

TDM

ANA.MIC

Headset

microphone

I2C.SR.SCL

I2C.CNTL.SDA

I2C.CNTL.SCL

PCM.VCK

PCM.VDR

PCM.VDX

PCM.VFS

I2S.CLK

I2S.SYNC

I2S.DIN

I2S.DOUT

MIC.MAIN.P

MIC.MAIN.M

MIC.SUB.P

DIG.MIC.0

MIC.SUB.M

DIG.MIC.1

HSMIC.P

HSMIC.M

Table 2-2. Signal Description (continued)

Description

Type(1) Ball

Configuration By Default After Reset

Released

Signal

Type(1)

Internal

Pull or Not

System enable output

OD/I

C13 SYSEN

OD

PU

Clock enable

O

C6 CLKEN

O

Clock enable 2

O

D7 CLKEN2

O

Clock request

I

G10 CLKREQ

I

PD

Output interrupt line 1

O

F10 INT1

O

Output interrupt line 2

O

F9 INT2

O

Output control the NRESPWRON

of the application processor

O

A13 NRESPWRON

O

Input, detect user action on the

reset button

I

B13 NRESWARM

I

Input, detect a control command to

start or stop the system

I

A11 PWRON

I

Not connected

B14 NC

Sleep request from device 1

I

P7 NSLEEP1

I

Sleep request from device 2

I

G9 NSLEEP2

I

Control for 256 Ã FS CLK output

O

D13 CLK256FS

O

Digital voltage scaling linked with

VDD1

I

F8 VMODE1

I

Boot pin 0

I

K11 BOOT0

I

PD

Boot pin 1

I

J11 BOOT1

I

PD

Enable signal for external LDO

OD

A10 REGEN

OD

PU

Security and digital rights

management

I

H8 MSECURE

I

Reference voltage

Power N16 VREF

Power

Analog ground for reference

voltage

Power

GND

N15 AGND

Power GND

Not connected

SmartReflex I2C data

I/O

C4

Signal not

functional(4)

Digital voltage scaling linked with

VDD2

I

D6 VMODE2

I

SmartReflex I2C data

I/O

GP I2C data

I/O

D4 I2C.CNTL.SDA

I/O

PU

GP I2C clock

I/O

D5 I2C.CNTL.SCL

I/O

PU

Data clock (voice port)

I/O

R1 PCM.VCK

I/O

Data receive (voice port)

I/O

T2 PCM.VDR

I/O

Data transmit (voice port)

I/O

T15 PCM.VDX

I/O

Frame synchronization (voice port) I/O

R16 PCM.VFS

I/O

Clock signal (audio port)

I/O

L3 I2S.CLK

I/O

Synchronization signal (audio port) I/O

K6 I2S.SYNC

I/O

Data receive (audio port)

I

K4 I2S.DIN

I

Data transmit (audio port)

O

K3 I2S.DOUT

O

Main microphone left input (P)

I

E2 MIC.MAIN.P

I

Main microphone left input (M)

I

F2 MIC.MAIN.M

I

Main microphone right input (P)

I

G2 MIC.SUB.P

I

Digital microphone 0 input data

I

Main microphone right input (M)

I

H2 MIC.SUB.M

I

Digital microphone 1 input data

I

Headset microphone input (P)

I

E3 HSMIC.P

I

Headset microphone input (M)

I

F3 HSMIC.M

I

Unused

Features(2)

Floating

Floating

Floating

GND

Floating

Floating

Floating

GND

VBAT

Floating

GND

GND

Floating

GND

N/A

N/A

Floating

N/A

N/A

GND

Floating

GND

N/A

N/A

Floating

GND

Floating

Floating

Floating

Floating

GND

Floating

Cap to GND

Cap to GND

Cap to GND

Cap to GND

Cap to GND

Cap to GND

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Terminal Description

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